Computer system including a novel address translation mechanism

Details Computer system including a novel address translation mechanism Computer system including a novel address translation mechanism

1999-06-01

2002-09-03

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S209000, C710S049000

Reexamination Certificate

active

06446189

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to processors and computer systems, and more particularly to address translation mechanisms used within computer systems and processors.
2. Description of the Related Art
A typical computer system includes a processor which reads and executes instructions of software programs stored within a memory system. In order to maximize the performance of the processor, the memory system must supply the instructions to the processor such that the processor never waits for needed instructions. There are many different types of memory from which the memory system may be formed, and the cost associated with each type of memory is typically directly proportional to the speed of the memory. Most modern computer systems employ multiple types of memory. Smaller amounts of faster (and more expensive) memory are positioned closer to the processor, and larger amounts of slower (and less expensive) memory are positioned farther from the processor. By keeping the smaller amounts of faster memory filled with instructions (and data) needed by the processor, the speed of the memory system approaches that of the faster memory, while the cost of the memory system approaches that of the less expensive memory.
Most modern computer systems also employ a memory management technique called “virtual” memory which allocates memory to software programs upon request. This automatic memory allocation effectively hides the memory hierarchy described above, making the many different types of memory within a typical memory system (e.g., random access memory, magnetic hard disk storage, etc.) appear as one large memory. Virtual memory also provides for isolation between different programs by allocating different physical memory locations to different programs running concurrently.
Early x86 (e.g., 8086/88) processors used a segmented addressing scheme in which a 16-bit segment value is combined with a 16-bit offset value to form a 20-bit physical address. In a shift-and-add operation, the 16-bit segment portion of the address is first shifted left four bit positions to form a segment base address. The 16-bit offset portion is then added to the segment base address, producing the 20-bit physical address. In the early x86 processors, when the shift-and-add operation resulted in a physical address having a value greater than FFFFFh, the physical address value “wrapped around” and started at 00000h. Programmers developing software for the early x86 processors began to rely upon this address wrap-around “feature”. In order to facilitate software compatibility, later x86 processors included an address bit
20
“masking” feature controlled by an “A20M” input pin. By asserting an A20M signal coupled to the A20M pin, address bit
20
is produced having a logic value of “0”. As a result, address values greater than FFFFFh appear to wrap around and start at 00000h, emulating the behavior of the early x86 processors.
Many modem processors, including x86 processors, support a form of virtual memory called “paging”. Paging divides a physical address space, defined by the number of address signals generated by the processor, into fixed-sized blocks of contiguous memory called “pages”. If paging is enabled, a “virtual” address is translated or “mapped” to a physical address. For example, in an x86 processor with paging enabled, a paging unit within the processor translates a “linear” address produced by a segmentation unit to a physical address. If an accessed page is not located within the main memory unit, paging support constructs (e.g., operating system software) load the accessed page from secondary memory (e.g., magnetic disk) into main memory. In x86 processors, two different tables stored within the main memory unit, namely a page directory and a page table, are used to store information needed by the paging unit to perform the linear-to-physical address translations.
Accesses to the main memory unit require relatively large amounts of time. In order to reduce the number of required main memory unit accesses to retrieve information from the page directory and page table, a small cache memory system called a translation lookaside buffer (TLB) is typically used to store the most recently used address translations. As the amount of time required to access an address translation in the TLB is relatively small, overall processor performance is increased as needed address translations are often found in the readily accessible TLB.
A typical modem processor includes a cache memory unit coupled between an execution unit and a bus interface unit. The execution unit executes software instructions. The cache memory unit includes a relatively small amount of memory which can be accessed very quickly. The cache memory unit is used to store instructions and data (i.e. data items) recently used by the execution unit, along with data items which have a high probability of being needed by the execution unit in the near future. Searched first, the cache memory unit makes needed information readily available to the execution unit. When needed information is not found in the cache memory unit, the bus interface unit is used to fetch the needed information from a main memory unit located external to the processor. The overall performance of the processor is improved when needed information is often found within the cache memory unit, eliminating the need for time-consuming accesses to the main memory unit.
FIG. 1
is a block diagram illustrating an address translation mechanism of an exemplary modem x86 computer system. A cache unit
10
within an x86 processor may be used to store instructions and/or data (i.e., data items) recently used or likely to be needed by an execution unit coupled to cache unit
10
. Cache unit
10
includes a TLB
12
used to store the most recently used address translations, a multiplexer
14
, and gating logic
16
.
TLB
12
receives a linear address provided to cache unit
10
and produces a stored physical address corresponding to the linear address. Multiplexer
14
receives the linear address provided to cache unit
10
and the physical address produced by TLB
12
. Multiplexer
14
produces either the physical address or the linear address dependent upon a PAGING signal. When paging is disabled, the linear address provided to cache unit
10
is a physical address, and address translation by TLB
12
is unnecessary. In this case, the PAGING signal is deasserted, and multiplexer
14
produces the linear address. When paging is enabled, the linear address provided to cache unit
10
is a virtual address, and translation of the virtual address to a physical address is necessary. In this case, the PAGING signal is asserted, and multiplexer
14
produces the physical address produced by TLB
12
. If a stored physical address corresponding to the linear address is found within TLB
12
, TLB
12
asserts a TLB HIT signal. Otherwise, the TLB hit signal is deasserted.
Gating logic
16
receives address bit
20
(i.e., signal A
20
) of the physical address produced by multiplexer
14
, and the A20M signal. Gating logic
16
produces a new signal A
20
dependent upon the A20M signal. When the A20M signal is deasserted, gating logic produces the new signal A
20
such that the new signal A
20
has the same value as the signal A
20
of the physical address produced by multiplexer
14
. In other words, when signal A20M is deasserted, gating logic “passes” the signal A
20
of the physical address produced by multiplexer
14
. On the other hand, when the A20M signal is asserted, gating logic produces the new signal A
20
with a logic value of “0”. In other words, when signal A20M is asserted, gating logic “masks” or “clears” the signal A
20
of the physical address produced by multiplexer
14
.
In addition to TLB
12
, cache unit
10
includes a cache memory
18
for storing the data items recently used or likely to be needed by the execution unit coupled to cache unit
10
. Cache memory
14
includes a tag array
20
for storing physical address “tags”

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