Computer system including a first level write-back cache and a s

Details Computer system including a first level write-back cache and a s Computer system including a first level write-back cache and a s

1996-06-17

1998-07-07

Kim, Matthew M.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711122, 711143, G06F 1208

Patent

active

057784337

ABSTRACT:
An apparatus for monitoring and decoding processor bus cycles and flushing a second level cache upon decoding a special flush acknowledge cycle. The CPU preferably includes an internal cache and a flush input for receiving a signal commanding the CPU to flush its internal cache. After flushing its cache by performing any necessary cycles to write back dirty data to main memory, the CPU performs a special flush acknowledge cycle to inform external devices that the flush procedure has been completed. A cache controller detects the flush acknowledge cycle and provides a flush signal to the second level cache. The cache controller then provides an end of cycle signal to the CPU to indicate that the flush cycle has been acknowledged.

REFERENCES:
patent: 4755930 (1988-07-01), Wilson, Jr. et al.
patent: 5241681 (1993-08-01), Hamid et al.
patent: 5276848 (1994-01-01), Gallagher et al.
patent: 5307477 (1994-04-01), Taylor et al.
patent: 5317720 (1994-05-01), Stamm et al.
patent: 5355467 (1994-10-01), MacWilliams et al.
patent: 5581727 (1996-12-01), Collins et al.
Pentium Processor User's Manual vol. 1: Pentium Processor Data Book Bus Functional Description, pp. 6-1 to 6-52, 1993.

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