Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2006-11-14
2006-11-14
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C710S004000, C710S036000, C710S052000
Reexamination Certificate
active
07136980
ABSTRACT:
A mechanism and method for maintaining cache consistency in computer systems that implements synchronized broadcasts using skew control and queuing. An access right corresponding to a given block allocated in a first active device may be configured to transition in response to a corresponding data packet being received through a data network. Additionally, transitions in ownership of the given block may occur at a different time than the time at which the access right to the given block is changed. To implement synchronized broadcasts, the address and data networks are configured such that a maximum amount of time from when a given broadcast packet conveyed on the address network arrives at a first active device to a time when the given broadcast packet arrives at a second active device is less than or equal to a minimum amount of time from when a data packet sent on the data network from the first active device arrives at the second active device. Each of the active devices may further comprise a queue control circuit coupled to an address-in queue and a data-in queue. The queue control circuit may be configured to prevent processing of a particular data packet that arrived in the data-in queue until all address packets that arrived earlier in the address-in queue are processed.
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Cypher Robert E.
Hill Mark D.
Wood David A.
Bataille Pierre-Michel
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Sun Microsystems Inc.
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