Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2008-03-18
2008-03-18
Mai, Son L. (Department: 2827)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C711S005000, C711S154000, C711S167000
Reexamination Certificate
active
07345901
ABSTRACT:
A computer system having a memory system, the memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. Access timing on each memory chip is determined by a self time block on each memory chip.
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Bartley Gerald Keith
Becker Darryl John
Dahlen Paul Eric
Germann Philip Raymond
Maki Andrew Benson
International Business Machines - Corporation
Mai Son L.
Williams Robert R.
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