Computer system having an interrupt handler

Details Computer system having an interrupt handler Computer system having an interrupt handler

1998-12-23

2001-04-24

Beausoleil, Robert (Department: 2181)

Electrical computers and digital data processing systems: input/

Interrupt processing

Multimode interrupt processing

C710S263000, C710S266000

Reexamination Certificate

active

06223246

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a computer system having an interrupt processing capability and more particularly to a computer system having an interrupt process capability therein independent of an operating system (hereinafter may be referred to as OS).
2. Description of Related Art
When the application system executed by microprocessors or the like becomes very large-scaled, there may be necessitated an exceptional process therefor. However, the performance of an OS and tasks managed by the OS is statically determined by the specifications of the real-time OS, thus it is rather difficult to change the predetermined performance. Moreover, it may become necessitated that some additional features be added to the application program. For example, a message in the midst of a message queue managed by the OS need be transferred to a task under a certain specific condition without contents of the task being altered. In such a case, the OS according to the related art does not allow for the message to be transferred to the task ignoring the order of transfer stored in the queue.
FIG. 1
is a block diagram showing a configuration example of related-art computer system. Referring to
FIG. 1
, a control unit
22
performing various processes is connected to a communication medium
21
. The control unit
22
executes a real-time OS
3
and thus executes application programs such as a task
4
1
through
4
n.
Data
51
, data
52
, data
53
and so on are stored in the message queue
23
in the control unit
22
. Task
41
receives data transmitted from a task which is being executed in another control unit (not shown), by way of the communication medium
21
. The real-time OS
3
is managed in such a manner that the data transferred is stored to the message queue
23
. How to manage the messages varies depending on the specifications of the real-time OS
3
in question. For example, the messages are managed and ordered in a first-in first-out (FIFO) fashion.
Referring to
FIG.1
, the FIFO method is carried out as follows: The real-time OS
3
receives a message request from among tasks
4
1
through
4
n
. Assume now for convenience that the task
4
1
requests a message. Then, the real-time OS
3
hands over data to the requesting task
4
1
in the order in which the message is received by the real-time OS
3
. If there exists undefined data which requires an interrupt process, the real time OS
3
and task
4
1
perform as follows (see FIG.
2
).
FIG. 2
is a flow chart showing processes of the real-time OS
3
and task when there exists, among messages requested by the task, an undefined datum which requires the interrupt process. Referring to
FIG. 2
, the task
4
1
requests the real-time OS
3
to re-send a message to the effect that the message received from the real-time OS
3
is not what the task
4
1
requested, that is, an undefined datum. Then, the real-time OS
3
performs a message re-sending process (STEP S
901
). Next, the real-time OS
3
adds a message obtained as a result thereof to the tail of a message queue
23
(STEP S
902
). Next, the real-time OS
3
removes a message in the head of the message queue
22
(STEP S
903
). Next, the task
4
1
determines whether or not the removed message is the one requested to be re-sent (STEP S
904
). When the removed message is found to be the one requested to be re-sent, the real-time OS
3
transfers the re-sent message to the task
4
1
(STEP S
905
). When the STEP S
904
determines that the removed message is not the one requested to be re-sent, the process returns to STEP S
902
for another processing.
If there are many messages stored in the message queue
23
, performing such a process mentioned above takes time such that the processing time increases proportional to the number of messages stored. It takes time until the task receives the message which is requested to be re-sent, thus deteriorating the responsibility of computer system.
Moreover, it is not possible for the task to predict in advance how many messages are put in the message queue
23
. It is also not possible to predict the degree to which the responsibility is deteriorated thereby.
Accordingly, in the computer system according to the related art, the development of another extra operating system is needed in order that an exceptional procedure can be achieved to change the OS and task. On the other hand, the task related thereto need be changed if the task is to be changed without implementing the extra operating system. Thus, the amount of tasks to be changed becomes enormous, thus deteriorating productivity of software therefor.
Moreover, various events occur as the application program becomes huge. Thereby, it becomes necessary to carry out a process responsive to each condition due to combination of the events, so that the event management becomes complicated.
Moreover, the increased processing time is required to recognize such conditions. Consider a case where limited is the time required for carrying out the process responsive to certain condition after the event such as a message re-sending request occurs. In this case, the increase in processing time not only results in deterioration of responsibility but also may cause a fatal outcome, for example, in terms of safety in an application system where a system need be stopped to secure safety in the event that a certain condition occurs.
SUMMARY OF THE INVENTION
In view of the foregoing drawbacks, it is therefore an object of the present invention to provide a computer system as wells as a control method therefor capable of handling exceptional procedures by performing interrupt processes with desirable responsibility so that making changes in the operating system and tasks are avoided and a simple configuration is achieved.
According to one preferred embodiment of the present invention, there is provided a control method for the computer system having interrupt capability therein, comprising the steps of: referring to at least one flag pattern in an interrupt activation condition flag storing unit which stores an event as an interrupt activation condition flag; thereafter determining whether or not the flag pattern exists in an operational key description storing unit which stores the position for the operation corresponding to the flag pattern in the interrupt activation condition flag storing unit; performing the interrupt process based on an operational description storing unit which stores a process corresponding to the flag pattern, in the event that there exists such the flag pattern as a result of the determining step; and thereafter resetting a bit of the flag corresponding to the process executed.
According to the configuration realizing such a control method, a flag operation is carried out in accordance with an event that occurs such that the interrupt process is performed responsive to this flag pattern. Thereby, making undue changes in the operating system as well as in tasks such as an application program are avoided so as to achieve a simple configuration. Thus, exceptional procedures can be handled by the interrupt processes with desirable responsibility.


REFERENCES:
patent: 5771374 (1998-06-01), Burshtein et al.
patent: 5790872 (1998-08-01), Nozue et al.
patent: 5850555 (1998-12-01), Qureshi et al.
patent: 5857108 (1999-01-01), Hong
patent: 5875341 (1999-02-01), Blank et al.
patent: 5894577 (1999-04-01), MacDonald et al.
patent: 6003109 (1999-12-01), Caldwell et al.

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