Electrical computers and digital data processing systems: input/ – Access arbitrating – Hierarchical or multilevel arbitrating
Reexamination Certificate
1998-06-08
2002-02-12
An, Meng-Ai T. (Department: 2783)
Electrical computers and digital data processing systems: input/
Access arbitrating
Hierarchical or multilevel arbitrating
C710S119000, C710S100000, C710S113000, C710S240000
Reexamination Certificate
active
06347352
ABSTRACT:
TECHNICAL FIELD
The present invention relates to computer architecture, and more particularly, to interfacing computer system components with a computer bus in an efficient manner.
BACKGROUND OF THE INVENTION
A computer system includes a set of interconnected components or modules of three basic types: central processing unit (CPU), memory, and input/output (I/O). The modules of the computer system are connected together by communication pathways known as busses. A bus is a shared transmission medium in that plural computer modules can transmit across the same bus. However, if two modules transmit during the same time period, their signals will overlap and become garbled. Therefore, it is important to ensure that only one module transmits across the bus during a given time period.
As shown in
FIG. 1
, a typical prior art computer system
10
includes a tiered arrangement of computer modules. The computer system
10
includes a multiprocessor system architecture in which first and second computer processors
12
,
14
are each coupled to a processor bus
16
. The computer system
10
also includes a bus agent
18
that interfaces computer system modules to the processor bus
16
. Coupled to the bus agent
18
is a main memory
20
, such as random access memory (RAM) and/or read-only memory (ROM). Also coupled to the bus agent
18
is a Peripheral Component Interconnect (PCI) bus
22
which is coupled to a PCI/ISA bridge
24
and a video controller
26
. The PCI/ISA bridge
24
interfaces an Industry Standard Architecture (ISA) bus with the PCI bus
22
. Coupled to the ISA bus
28
are a hard drive
30
and a fax/modem
32
.
A major problem with the tiered architecture of prior art computer systems, such as the computer system
10
shown in
FIG. 1
, is that such computer systems are unable to keep pace with the ability of the computer system modules to generate requests for use of the processor bus
16
. The speed of the computer system
10
is limited by the bottleneck created at each tier of the computer system. For example, for the hard drive
30
to transmit a transaction to the computer processor
12
, the hard drive must first arbitrate with the fax/modem
32
for use of the ISA bus
28
. After gaining access to the ISA bus
28
, the transaction from the hard drive
30
is passed to the PCI/ISA bridge
24
. The PCI/ISA bridge
24
arbitrates with the video controller
26
for use of the PCI bus
22
. After gaining access to the PCI bus
22
, the PCI/ISA bridge
24
transmits the transaction from the hard drive
30
to the bus agent
18
via the PCI bus as a bus request for use of the processor bus
16
. The bus agent
18
then arbitrates between the bus request from the PCI bus
22
and any bus request from the memory
20
and selects one of the bus requests for transmission of its associated transaction on the processor bus
16
. As a result, a single transaction from the hard drive
30
must undergo arbitration for use of three separate computer buses in order for the transaction to reach the processor
12
. Moreover, the transaction from the hard drive
30
prevents the main memory
20
, video controller
26
, and fax/modem
32
from using the processor bus
16
, PCI bus
22
, and ISA bus
28
.
An alternate prior art computer system
40
is shown in FIG.
2
. The computer system
40
shown in
FIG. 2
is substantially identical to the computer system
10
shown in
FIG. 1
, except that the computer system
40
includes a second bus agent
42
. The second bus agent
42
couples the main memory
20
to the processor bus
16
. Such an arrangement does not greatly effect the speed of the computer system because bus requests from the memory
20
or the PCI bus
22
still have to be arbitrated before being transmitted on the processor bus
16
. The difference is that the arbitration is performed between the first bus agent
18
and the second bus agent
40
in
FIG. 2
rather then within the first bus agent
18
as in FIG.
1
. Moreover, the bus agent
18
, PCI bus
22
, PCI/ISA bridge
24
, video controller
26
, ISA bus
28
, hard drive
30
and fax/modem
32
are still arranged in a tiered structure. Accordingly, the computer system
40
shown in
FIG. 2
suffers from the same speed drawbacks as the computer system
10
shown in FIG.
1
.
SUMMARY OF THE INVENTION
The present invention is directed to a computer system, method, and controller bus agent for controlling access to a computer bus. The computer system includes at least three bus requesters from which transactions are transmitted to the computer bus. A first bus agent is coupled to the computer bus and to one or more of the bus requesters. The computer system also includes a second bus agent coupled to the computer bus. The second bus agent includes a plurality of bus requester ports, with each bus requester port being coupled to one of the bus requesters. As such, the computer system includes a relatively flat architecture by employing plural bus agents and plural bus requesters coupled to separate ports of at least one of the bus agents. Such a relatively flat architecture enables the computer system to handle bus requests in parallel rather than the serial, tiered approach of the prior art.
The controller bus agent of the present invention controls access to the computer bus of the computer system. The controller bus agent preferably includes an internal arbiter structured to receive bus requests from each of a plurality of bus requesters and select one of the bus requests based on an internal arbitration algorithm. The controller bus agent also includes an external arbiter coupled to the computer bus, the internal arbiter, and another bus agent. The external arbiter is structured to arbitrate between the bus request selected by the internal arbiter and a bus request received from the other bus agent such that the external arbiter selects one of the bus requests for transmission on the computer bus. Employing a controller bus agent with internal and external arbiters enables the computer system to have a relatively flat architecture rather than the tiered architecture of the prior art computer systems.
The method of the present invention also controls access to the computer bus of the computer system. The method receives bus requests from each of a plurality of bus requesters at a controller bus agent. The controller bus agent selects one of the bus requests received from the bus requesters based on an internal arbitration algorithm. The controller bus agent also receives a bus request from another bus agent. The method includes arbitrating between the bus request selected by the internal arbiter and the bus request received from the other bus agent such that one of the bus requests is selected for transmission on the computer bus.
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M. Morris Mano,Computer System Architecture(Second Edition), Prentice-Hall, Inc. 1982, pp. 406-415 and pp. 454-462.
Jeddeloh Joe
Klein Dean A.
An Meng-Ai T.
Ciccozzi John
Dorsey & Whitney LLP
Micron Electronics Inc.
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