Computer system having a data buffering system which includes a

Details Computer system having a data buffering system which includes a Computer system having a data buffering system which includes a

1997-07-23

1999-09-07

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

710 56, 711109, 711110, 711117, G06F 1208, G11C 804

Patent

active

059480823

ABSTRACT:
Disclosed is a computer system having a ring buffer arrangement which includes a plurality of sub-rings and a main ring. Each of the sub-rings includes a plurality of buffer memories and the main ring includes a plurality of the sub-rings. A main write pointer and a main read pointer are provided for the main ring in order to indicate a sub-ring for which data writing and data reading are currently being performed respectively. A sub-write pointer and a sub-read pointer are provided for each sub-ring in order to indicate, for the sub-ring, a buffer memory for which data writing and data reading are currently being executed respectively. Since the total size of the double ring buffer is large, not all of the buffer memories can be resident in physical memory. However, since the number of buffer memories included in a single sub-ring is relatively small, one sub-ring can be resident in the physical memory. When writing to, and reading from, the buffer synchronously, data buffering is performed by only using one sub-ring to avoid swapping the buffer memories.

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IBM Technical Information Bulletin, vol. 24 No. 11A pp. 5716-5723, Terrill et al.: "Random-access Memory Beamformer", Nov. 1981.
IBM Technical Information Bulletin, vol. 23 No. 11 pp. 5033-5039, Terrill et al.: "Random-access Memory Implementation of a Beamformer", Apr. 1981.
IBM Technical Information Bulletin, vol. 20 No. 8 pp. 3309-3310, Chapman et al.: "Data Management in a Circular Buffer", Jan. 1978.

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