Computer system for supporting increased PCI master devices...

Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation

Reexamination Certificate

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Details

C710S107000, C710S113000, C710S040000, C370S465000

Reexamination Certificate

active

06199123

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to microprocessor based computer systems having a peripheral component interconnect, or PCL bus.
2. Description of the Related Art
Computer system complexity in microprocessor based computers has been increasing at a very rapid rate. As computer system complexity has increased, more and more processing power has been placed in peripheral devices. The purpose of this has been to transfer some of the computational workload from the microprocessor central processing unit (or CPU) to the peripheral devices.
The computational workload has been increasingly transferred to what are known as masters. In a commercial desktop personal computer system, example master devices would typically include network controllers, disk controllers (such as SCSI devices) and video controllers. The peripheral component interconnect (or PCI) bus has allowed a certain number of peripheral devices to connect to the central processing unit. Each PCI master device has required its own assigned signal pair (REQ# and GNT#) to arbitrate for the PCI bus. Existing PCI chipsets have provided a fixed number of such signal pairs, usually ten. This has in effect limited the number of PCI masters in the computer system.
The number of masters could be increased via a bridge chip, called either a PCI-to-PCI or P2P bridge chip. P2P bridge chips have in effect added a second PCI bus for a computer system, commonly known as a secondary PCI bus. The P2P bridge chip functions as a master or primary PCI bus, controlled by the core logic chipset while acting as a controller for the secondary PCI bus. Each P2P bridge permitted an additional nine master devices on a secondary PCI bus.
However, all master devices communicating with the computer system through a P2P chip have suffered in performance, usually in terms of bus access time or latency. P2P bridges have also increased system cost. Further, when there were only a few additional or extra master devices required, the additional expense of the bridge chip has caused cost concerns.
SUMMARY OF THE INVENTION
Briefly, the present invention provides a new and improved computer system which has a processor and a main memory. The computer system also includes a bus and a plurality of peripheral devices. In the preferred embodiment, the bus is a peripheral component interconnect or (PCI) bus and the peripheral devices are PCI master devices. A bridge selectively connects the bus to the processor main memory and a signal pair connects a peripheral device to the bridge. A logic circuit is provided to connect two of the peripheral devices to a single signal pair. The logic circuit performs local arbitration of requests from the peripheral devices for access to the signal pair. In this manner, the number of peripheral devices is not limited to the number of signal pairs available. More peripheral devices are afforded access through the bridge. Multiple PCI devices thus may arbitrate for control of the PCI bus while still appearing to software to be resident on the primary PCI bus. This is further accomplished without the need for a PCI-to-PCI bridge chip.


REFERENCES:
patent: 4596390 (1986-06-01), Studley
patent: 5796961 (1998-08-01), O'Brien
patent: 5940403 (1999-08-01), Williams
patent: 5956493 (1999-09-01), Hewitt et al.
patent: 5959869 (1999-09-01), Miller et al.
patent: 5999533 (1999-12-01), Peres et al.
Intel, Bridge Products -21554 Embedded PCI-to-PCI Bridge, Aug. 19, 1999, pp. 1-3.
Intel, 21050 PCI-to-PCI Bridges, Oct. 1998, pp. 1-5.

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