Computer system for preventing cache malfunction by invalidating

Details Computer system for preventing cache malfunction by invalidating Computer system for preventing cache malfunction by invalidating

1997-08-26

1999-08-03

Lee, Thomas C.

Electrical computers and digital processing systems: support

Computer power control

Power conservation

713322, 713400, 711141, G06F 132

Patent

active

059319518

ABSTRACT:
When a CPU enters the sleep mode, an L2 cache with the ZZ terminal is also switched to the sleep mode simultaneously. When the CPU returns from the sleep mode, the L2 cache is simultaneously switched from the sleep mode to the normal operation mode. Since the normal operation of the cache is not ensured for a fixed period of time from when it leaves the sleep mode, the cache is placed in the disabled state in which its use is prohibited before being switched to the sleep mode and returned to the enabled state in which its use is allowed after a lapse of a fixed period of time from when it leaves the sleep mode.

REFERENCES:
patent: 5486726 (1996-01-01), Kim et al.
patent: 5630146 (1997-05-01), Conary et al.
patent: 5724611 (1998-03-01), Evoy
patent: 5813022 (1998-09-01), Ramsey et al.

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