Electrical computers and digital processing systems: memory – Address formation – Address multiplexing or address bus manipulation
Reexamination Certificate
1997-10-28
2001-06-05
Yoo, Do (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address multiplexing or address bus manipulation
C711S214000, C712S205000
Reexamination Certificate
active
06243798
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to processors, and more specifically, to a system and method for allowing a two word “jump” instruction to be executed in the same number of cycles as a single word “jump” instruction, thereby allowing a processor system to increase addressable memory space without reducing performance.
2. Background of the Invention
Presently, in some processor systems, all instructions are single word instructions. This means that a single word is used to inform the processor of each specific operation to be performed. A problem with single word instructions is that they limit the amount of addressable memory space since single word instructions only have a limited number of address bits.
In order to increase the addressable memory space, some processor systems implement a paging scheme in the program memory. In a paging scheme, the program memory is divided into a plurality of pages. A bit or bits in a data file location will indicate which page in the program memory is currently being accessed. The problem with paging schemes is that in order to access data in a different page (i.e., a page different from the currently selected page) the bit or bits in the data file location need to be changed. This creates a lot of problems for the end user especially if a programmer did not properly change the data file bit(s) when required.
Therefore, a need exists to provide a system for increasing the addressable memory space to be used by a processor. The system must increase the addressable memory space to be used by the processor without reducing the overall performance of the processor. The system must increase the addressable memory space without using a paging scheme and without reducing the overall performance of the processor. The system must increase the addressable memory space without reducing the overall performance of the processor by allowing two word jump instructions to be executed in the same number of cycles as a single jump instruction.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, it is an object of the present invention to provide a system for increasing the addressable memory space to be used by a processor.
It is another object of the present invention to provide a system for increasing the addressable memory space to be used by the processor without reducing the overall performance of the processor.
It is still another object of the present invention to provide a system that increases addressable memory space without using a paging scheme and without reducing the overall performance of the processor.
It is still another object of the present invention to provide a system that increases the addressable memory space to be used by a processor without reducing the overall performance of the processor by allowing two word jump instructions to be executed in the same number of cycles as a single word jump instruction.
BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS
In accordance with one embodiment of the present invention, a system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction thereby allowing a processor system to increase memory space without reducing performance is disclosed. The system utilizes a linearized program memory for storing instructions to be executed by the processor system. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be executed by the processor system to the linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to an output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word jump instruction on the first address bus after an address of an operand of a first word of the two word jump instruction has been placed on the first address bus. This allows for a full address value of the two word jump instruction to be sent to the linearized program memory in the same number of cycles as a single word jump instruction.
In accordance with another embodiment of the present invention, a method is disclosed which allows for a two word jump instruction to be executed in the same number of cycles as a single word ump instruction, thereby allowing a processor system to increase memory space without reducing performance. The method comprises the steps of providing a linearized program memory for storing instructions to be executed by the processor system; providing a first address bus coupled to the linearized program memory for sending the addresses of the instructions to be executed by the system to the linearized program memory; providing a pointer coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of a current instruction in the linearized program memory to be fetched on the first address bus; and providing a second address bus having one end coupled to an output of the program memory and a second end coupled to the first address bus for placing an address of an operand of a second word of the two word jump instruction on the first address bus after a address of an operand of a first word of the two word jump instruction has been placed on the first address bus thereby providing a full address value of the two word jump instruction in the same number of cycles as a single word jump instruction to the linearized program memory.
The foregoing and other objects, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiments of the invention, as illustrated in the accompanying drawing.
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Allen Steve
Chiao Jennifer
Drake Rodney J.
Triece Joseph W.
Wojewoda Igor
Baker & Botts L.L.P.
Microchip Technology Incorporated
Portka Gary J.
Yoo Do
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