Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-10-17
2004-04-13
Elmore, Reba I. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S136000, C711S159000, C711S160000
Reexamination Certificate
active
06721852
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to processor-based systems, and, more particularly, to updating a directory cache in a distributed, shared-memory processor-based system.
2. Description of the Related Art
Businesses typically rely on network computing to maintain a competitive advantage over other businesses. As such, developers, when designing processor-based systems for use in network-centric environments, may take several factors into consideration to meet the expectation of the customers, factors such as functionality, reliability, scalability, and performance of such systems.
One example of a processor-based system used in a network-centric environment is a mid-range server system. A single mid-range server system may have a plurality of system boards that may, for example, be configured as one or more domains, where a domain, for example, may act as a separate machine by running its own instance of an operating system to perform one or more of the configured tasks.
A mid-range server, in one embodiment, may employ a distributed shared memory system, where processors from one system board can access memory contents from another system board. The union of all of the memories on the system boards of the mid-range server comprises a distributed shared memory (DSM).
One method of accessing data from other system boards within a system is to broadcast a memory request on a common bus. For example, if a requesting system board desires to access information stored in a memory line residing in a memory of another system board, the requesting system board typically broadcasts on the common bus its memory access request. All of the system boards in the system may receive the same request, and the system board whose memory address ranges match the memory address provided in the memory access request may then respond.
The broadcast approach for accessing contents of memories in other system boards may work adequately when a relatively small number of system boards are present in a system. However, such an approach may be unsuitable as the number of system boards grows. As the number of system boards grows, so does the number of memory access requests, thus to handle this increased traffic, larger and faster buses may be needed to allow the memory accesses to complete in a timely manner. Operating a large bus at high speeds may be problematic because of electrical concerns, in part, due to high capacitance, inductance, and the like. Furthermore, a larger number of boards within a system may require extra broadcasts, which could further add undesirable delays and may require additional processing power to handle the extra broadcasts.
Designers have proposed the use of directory caches in a distributed shared memory systems to reduce the need for globally broadcasting memory requests. Typically, each system board serves as home board for memory lines within a selected memory address range, and where each system board is aware of the memory address ranges belonging to the other system boards within the system. Each home board generally maintains its own directory cache for memory lines that fall within its address range. Thus, when a requesting board desires to access memory contents from another board, instead of generally broadcasting the memory request in the system, the request is transmitted to the appropriate home board. The home board may consult its directory cache and determine which system board is capable of responding to the memory request.
Directory caches are generally effective in reducing the need for globally broadcasting memory requests during memory accesses. However, implementing a directory cache that is capable of mapping every memory location within a system board generally represents a significant memory overhead. As such, directory caches are often designed to hold only a subset of the total memory. When a particular directory cache is full, old entries may be discarded or overwritten to make room for the new ones. However, updating a directory cache to replace old entries with new ones may prove computationally expensive, particularly when it is desirable to have access to the replaced entries in the near future.
SUMMARY OF THE INVENTION
In one aspect of the instant invention, an apparatus is provided for updating a directory cache. The apparatus comprises a control unit adapted to detect a memory access transaction, determine a retention value based on the type of memory access transaction, and store the retention value in an entry associated with the memory access transaction.
In another aspect of the present invention, a method is provided for updating a directory cache. The method comprises detecting a memory access transaction, determining a retention value based on the type of memory access transaction, and storing the retention value associated with the memory access transaction in the directory cache.
In yet another aspect of the instant invention, an article comprising one or more machine-readable storage media containing instructions is provided for updating a directory cache. The instructions, when executed, may enable a processor to perform coherence for memory transactions within a first system board set using a first coherence scheme. The instructions, when executed, may further enable the processor to perform coherence for memory transactions between the first system board set and a second system board set using a second coherence scheme, wherein the second coherence scheme employs a retention value associated with one or more entries stored in the directory cache to identify which entry to victimize when storing a new entry.
REFERENCES:
patent: 5664121 (1997-09-01), Cerauskis
patent: 5829033 (1998-10-01), Hagersten et al.
patent: 5911052 (1999-06-01), Singhal et al.
patent: 6243742 (2001-06-01), Hagersten et al.
patent: 6243794 (2001-06-01), Casamatta
patent: 6490654 (2002-12-01), Wickeraad et al.
patent: 6532520 (2003-03-01), Dean et al.
patent: 6542966 (2003-04-01), Crawford et al.
patent: 2002/0049889 (2002-04-01), Hoogerbrugge et al.
Phelps Andrew E.
Shanahan Patricia
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