Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1998-03-25
2001-06-12
Ellis, Kevin L. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S126000
Reexamination Certificate
active
06247102
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to computer systems and, more particularly, to integrated bus bridge designs for use in high performance computer systems. Still more particularly, the invention relates to the configuration and operation of a bus bridge to support multiple concurrent data transactions between a control processor, memory, a graphics controller and a peripheral bus.
2. Background of the Invention
Computer architectures generally include a plurality of devices interconnected by one or more buses. For example, conventional computer systems typically include a central processing unit (“CPU”) coupled through bridge logic to main memory. A CPU bus usually is provided to couple the CPU to the bridge logic and a memory bus is provided to couple the bridge logic to the main memory. A main memory controller typically is incorporated within the bridge logic to generate various control signals for accessing the main memory. An interface to a high bandwidth local expansion bus, such as the Peripheral Component Interconnect (“PCI”) bus, may also be included as a portion of the bridge logic. Examples of devices which can be coupled to the local expansion bus include network interface cards, video accelerators, audio cards, SCSI adapters, and telephony cards, to name a few. An example of such a bridge logic unit is described in U.S. Pat. No. 5,634,073, assigned to Compaq Computer Corporation, which includes interfaces to three busses—a CPU bus, memory bus, and a PCI bus.
An older-style expansion bus also may be supported through yet an additional bus interface to provide compatibility with earlier-version expansion bus adapters. Examples of such expansion buses include the Industry Standard Architectures (ISA) bus, the Extended Industry Standard Architecture (“EISA”) bus, and the Microchannel Architecture (MCA) bus. Various devices may be coupled to this second expansion bus including a fax/modem, sound card, keyboard and mouse.
It would be desirable for the bridge logic to link or interface more than the CPU bus, a peripheral bus such as a PCI bus, and the memory bus. In applications that are graphics intensive, a separate peripheral bus optimized for graphics related data transfers may be provided in the computer system. A popular example of such a bus is the Advanced Graphic Port (“AGP”) bus. The AGP bus is generally considered a high performance, component level interconnect bus optimized for three dimensional graphical display applications, and is based on a set of performance extensions or enhancements to the PCI standard. In part, the AGP bus was developed in response to the increasing demands placed on memory bandwidths for three dimensional renderings. With the advent of AGP, a graphics controller can be removed from the PCI bus (where it traditionally was located) to the AGP bus. AGP provides greater bandwidth for data transfer between a graphics accelerator and system memory than is possible with PCI or other conventional bus architectures. The increase in data rate provided by AGP allows some of the three dimensional rendering data structures, such as textures, to be stored in main memory, reducing the cost of incorporating large amounts of memory local to the graphics accelerator or frame buffer.
Although the AGP uses the PCI specification as an operational baseline, it provides three significant performance extensions or enhancements to that specification. These extensions include a deeply pipelined read and write operation, demultiplexing of address and data on the AGP bus, an alternating current (AC) timing for, e.g., 133 MHz data transfer rates. The bridge unit of U.S. Pat. No. 5,634,073 does not include an interface to an AGP bus.
Since computer systems were originally developed for business applications including word processing and spreadsheets, the bridge logic within such systems was generally optimized to provide the CPU with relatively good performance with respect to its access to main memory. The bridge logic generally provided relatively poor performance, however, with respect to main memory accesses by other devices residing on peripheral buses. Similarly, the bridge logic provided relatively poor performance with respect to data transfers between the CPU and peripheral buses as well as between peripheral devices interconnected through the bridge logic.
Recently, however, computer systems have been increasingly used in processing for various real time applications, including multimedia applications such as video and audio, telephony, and speech recognition. These systems require not only that the CPU have adequate access to the main memory, but also that devices residing on various peripheral buses such as an AGP bus and a PCI bus have fair access to the main memory as well. Furthermore, it is often important that transactions between the CPU, the AGP bus and the PCI bus be efficiently handled. Accordingly, the bus bridge logic for a modem computer system preferably should include mechanisms to efficiently prioritize and arbitrate among the varying requests of devices seeking access to main memory and to other system components coupled through the bridge logic.
In a computer system employing bridge logic coupling multiple buses, transactions between the various buses usually occur simultaneously. For example, the CPU may be writing data to main memory while a PCI master (a device coupled to the PCI bus controlling the operation of the bus) may be trying to supply data to a device on the CPU bus. Usually, a bus bridge processes one bus transaction at a time forcing all other transactions to wait their turn.
For the reasons discussed above, it would be advantageous to design a computer system that includes a bus bridge capable of coupling multiple buses and which attains high performance by allowing transactions between the buses to occur concurrently. Despite the advantages that such a system would offer, to date no such systems have been introduced.
SUMMARY OF THE INVENTION
The deficiencies of the prior art described above are solved in large part by a computer system including a bridge logic unit coupling together the CPU, the memory device, and multiple expansion buses. The CPU couples to the bridge logic unit via a CPU bus and the memory device couples to the bridge logic unit via a memory bus. In accordance with an exemplary embodiment of the present invention, one expansion bus is implemented as a peripheral component interconnect (“PCI”) bus and the other expansion bus comprises an accelerated graphics port (“AGP”) bus. The bridge logic unit (commonly referred to as a “North bridge”) generally routes bus cycle requests from one of the four buses (CPU, memory, PCI, AGP) to another of the buses while concurrently routing bus cycle requests to another pair of buses. By permitting concurrent flow of cycle requests (which generally include write and read requests) between the four buses, overall system performance can be significantly increased.
The bridge logic unit preferably includes a CPU interface, a memory controller, an AGP bus interface, and a PCI bus interface. Each pair of interfaces (including the memory controller) are separately coupled by at least one queue. The queues temporarily store write requests and/or read data. Accordingly, the bridge logic unit includes a plurality of write queues for storing write requests from one interface to another, and a plurality of read queues for storing read data from one interface to another. By way of example, the CPU, PCI, and AGP interfaces couple to the memory controller via write queues in which each interface can concurrently store (or “post”) memory write requests. The queues preferably provide the capacity to store two or more write requests (for the write queues) or read data streams (for the read queues).
Because each interface can communicate concurrently with all other interfaces (including t
Chin Kenneth T.
Coffee C. Kevin
Collins Michael J.
Johnson Jerome J.
Jones Phillip M.
Compaq Computer Corporation
Conley & Rose & Tayon P.C.
Ellis Kevin L.
Heim Michael F.
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