Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-06-26
2007-06-26
Peugh, Brian R. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C712S207000
Reexamination Certificate
active
10766698
ABSTRACT:
Various embodiments of a computer system employing bundled prefetching are disclosed. In one embodiment, a cache memory subsystem implements a method for prefetching data. The method comprises the cache memory subsystem receiving a read request to access a line of data and determining that a cache miss with respect to the line occurred. The method further comprises transmitting a bundled transaction on a system interconnect in response to the cache miss, wherein the bundled transaction combines a request for the line of data and a prefetch request. In response to the bundled transaction, the method further comprises determining that a second cache is an owner of the first line of data, determining whether the second cache is also an owner for any of the selected lines of data beyond the first line, the second cache transmitting to the first cache any of the selected lines for which the second cache is an owner, and the second cache transmitting a null-data packet to the first cache for each of a remainder of the selected lines of data for which the second cache is not an owner.
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Hagersten Erik E.
Wallin Dan G.
Bradley Matthew
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Peugh Brian R.
Sun Microsystems Inc.
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