Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies
Patent
1998-03-11
2000-08-29
Palys, Joseph E.
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Multiple or variable intervals or frequencies
713320, G06F 104, G06F 126, G06F 1100
Patent
active
061123099
ABSTRACT:
The object of the present invention is to balance power saving and useability in a computer system. According to a first aspect of the present invention, when predetermined activities of a device in a computer system, each of which occurs within a predetermined period t.sub.1 after the previous predetermined activity, succeed for a predetermined period t.sub.2 or longer, a substantial frequency of a central processing unit is raised. According to a second aspect of the present invention, a substantial frequency of the CPU is raised after a disk drive has been accessed, and if a predetermined activity performed by a device other than the disk drive occurs within a predetermined period t.sub.4 following the raise of the frequency, the substantial frequency of the CPU is lowered when a predetermined period t.sub.3, following the predetermined activity, has passed.
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patent: 5546568 (1996-08-01), Bland et al.
patent: 5590280 (1996-12-01), Watanbe
patent: 5625826 (1997-04-01), Atkinson
Advanced Power Management BIOS Interface Specification, Revision 1.2, Feb. 1996.
Inoue Tadanobu
Sekiya Kazuo
Dougherty Anne Vachon
International Business Machines Corp.
Martin Willie
Palys Joseph E.
Shofi David M.
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