Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1995-12-04
2001-03-27
Gossage, Glenn (Department: 2759)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S167000, C710S005000, C710S054000, C710S240000
Reexamination Certificate
active
06209067
ABSTRACT:
SPECIFICATION
1. Field of the Invention
The present invention relates to an apparatus And method of preventing a processor from starving a local bus master of memory access, and more particularly to holding off the processor from posting further cycles to its write post queues when the local bus master is requesting access to memory and access is denied because flushing the write post queues must occur before the local bus master memory access.
2. Description of the Related Art
Systems in which many devices share a common resource, such as a system bus or main memory, typically utilize arbitration schemes for allocating access to the resource under conditions during which a plurality of devices may concurrently request access. In modern computer systems, input/output (I/O) devices located on expansion buses such as the Industry Standard Architecture (ISA) or the Extended Industry Standard Architecture (EISA) are able to access the main memory through a mechanism commonly known as direct memory access (DMA). DMA allows data to be transferred between I/O devices and the main memory without having to go through the microprocessor, which frees up the microprocessor to perform other functions.
The ISA bus was originally developed to improve on the bus used in the original PC architecture developed by International Business Machines (IBM) Corporation (Armonk, N.Y.). ISA provided for a wider data bus and allowed for faster peripheral or I/O devices. However, as computer system components grew ever more powerful, ISA proved to be inadequate, which necessitated the development of the new bus EISA standard. Both ISA and EISA support DMA transfers, although the EISA bus allows I/O devices to access a 32-bit memory space and enables higher data transfer rates between the I/O devices and main memory.
More recently, a mezzanine bus architecture standard referred to as the Peripheral Component Interconnect (PCI) was developed to allow for connection of highly integrated peripheral components on the same bus as the processor/memory system. PCI provides a bus standard on which high performance peripheral devices, such as graphics devices and hard disk drives, can be connected with the processor/memory module, thereby permitting these high performance devices to avoid the general access latency and the bandwidth constraints that would have occurred if the devices were connected to standard I/O expansion buses such as EISA or ISA. The PCI subsystem comprising the processor/memory system and the high performance peripheral devices is typically coupled to an EISA expansion bus by a PCI-EISA bridge. Consequently, in a system including a PCI bus and an EISA bus, peripheral devices on both the EISA and PCI buses are capable of requesting access to the main memory. Requests from EISA bus masters in such a system are forwarded through the PCI-EISA bridge.
Due to the existence of the many I/O and peripheral devices in the computer system that may access the main memory at any time, contention for the main memory between the microprocessor and the other system devices is very likely. In addition, due to its size, the main memory is typically implemented with dynamic random access memories (DRAMs). Each word in a DRAM needs to be refreshed periodically to prevent data loss due to charge leakage. Refresh controllers, which are typically implemented as part of the memory controller, perform the refresh function by sequentially accessing address locations in the DRAMs. As long as the rate at which each address location is refreshed is above the minimum required rate, data integrity is assured. Thus, in addition to I/O requests, the microprocessor is also competing with the refresh controller for access to the main memory.
In most computer systems, the microprocessor is the most intensive user of the main memory. Therefore, it is desirable that the microprocessor be given the highest priority. However, the arbitration scheme must also recognize that the microprocessor must relinquish control of the memory under certain conditions to prevent starvation of the mezzanine and expansion buses. Consequently, the arbitration scheme must be capable of balancing the needs of the various competing devices so that the efficiency of the computer system is optimized.
SUMMARY OF THE INVENTION
A computer system according to the present invention has a memory controller that provides numerous performance increases, particularly in the PCI bus environment, and can readily work with numerous types and speeds of processors and different speed memory devices.
The memory controller provides a series of queues between the processor and the PCI bus and the memory system to allow deep write posting. In the preferred embodiment, four quadword addresses can be posted from the processor and eight quadword addresses from the PCI bus for write operations. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. In this way, all writes are completed prior to the read occurring, so that the main memory is coherent for the read operation from the PCI bus. When a PCI device executes a memory read, the processor cache and (L
2
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2
cache are snooped in parallel with the memory read operation. Data is not provided until the snoop operation is complete. If the snoop operation indicates a modified location, a writeback operation is performed before data is provided to the PCI bus. If data is coherent between the memory and caches, data is provided from the memory to the PCI bus. If the queues are not empty when the PCI device executes a memory read, the queues are flushed and the PCI device must retry the operation. A timer prevents further write posting to a processor to PCI queue to allow, on average, enough time for the PCI device to retry the read operation. However, more performance is desired from the processor, and therefore to maintain coherency a content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as that read operation of the processor. If so, the read operation is not executed until the PCI memory queue has cleared that entry. If no address hit occurs, the read operation is accepted and executed according to arbitration priority rules. Again, in this manner, the main memory is coherent prior to the read operation occurring. It is noted that allowing two write operations to the same address to be present in the two queues is not a problem and does not produce incoherent results, as the exact timing between the buses would never be clear in any event.
In the preferred embodiment the PCI bus capability of read ahead operations when a Memory Read Multiple has been requested is present. This allows the memory system to obtain data at a high rate and leave it posted for reading by the PCI bus master when indicated by the particular cycle. However, as noted in the background, it is possible that the PCI bus master would abort the cycle prior to its completion. To resolve this problem, a memory controller according to the preferred embodiment receives an abort signal from the PCI bus interface and as soon thereafter as can be done, while maintaining DRAM data integrity, terminates the read ahead cycle, even though the read ahead cycle has not fully completed. Thus, the read ahead cycle is aborted as soon as possible. Therefore, the full read ahead does not occur, so that the situation of an abort occurring during a read ahead operation does not overly hinder performance as would normally be the case.
To further improve the system, the memory controller of the preferred embodiment has improved prediction rules for determining when to precharge the DRAM devices. The prediction rules are based on whether the cycle is coming from the processor or is coming from the PCI bus. By using these new rules, more efficient precharging is done, and additionally, more page mod
Collins Michael J.
Larson John E.
Moriarty Michael P.
Ramsey Jens K.
Akin Gump Strauss Hauer & Feld & LLP
Compaq Computer Corporation
Gossage Glenn
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