Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
1998-03-12
2001-07-10
Beausoleil, Robert (Department: 2781)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S322000, C713S340000
Reexamination Certificate
active
06260151
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a computer system suitable for, for example, easy-to-carry information equipment for personal use, and more particularly to a computer system capable of reducing the unnecessarily consumed electric power remarkably.
One known method of controlling electric power in microprocessors mounted on conventional information equipment is to reduce the power consumption by decreasing the frequency of the clock or stopping the clock when the system is idling.
Another known method of decreasing the power consumption in the entire system is to reduce the power consumption by stopping the supply of power to the input/output devices that are presently out of use.
In the techniques realizing these methods, since the component parts to which the supply of power may be stopped are limited, the unnecessarily consumed power cannot be reduced sufficiently. For example, portable information equipment operating from the power supplied from a battery pack containing a secondary battery has encountered the problem of having to shorten the possible operating time of the system.
FIG. 1
shows the configuration of a conventional computer system. In the computer system, a power supply section
34
supplies electric power under the control of a power sequence controller
33
. In response to the control signal transmitted from a processor
10
via an IO bus
3
a
, an IO bus bridge
32
, and an IO bus
3
b
, the power sequence controller
33
controls the power supply section
34
.
In such a conventional computer system, for example, even when all the devices, including device
31
a
and device
31
b
, connected to the IO bus
3
a
have been out of operation for a long time, a command signal to stop the supply of power to the IO bus
3
a
is not transmitted to the power sequence controller
33
.
As described above, the conventional computer system has the following problem: the unnecessarily consumed power cannot be reduced sufficiently and therefore the possible operating time of the system has to be shortened in portable information equipment operating from the power supplied from, for example, a battery pack containing a secondary battery.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a computer system capable of reducing the unnecessarily consumed power remarkably by widening the scope of application of such power supply control as stopping the supply of power to devices that have been out of use for longer than a predetermined period of time.
According to one aspect of the present invention, there is provided a computer system comprising: a processor; a power sequence controller for controlling the supply of power of a power source in accordance with an inputted control signal; a control signal line for connecting the processor directly to the power sequence controller; and an interface circuit, provided in the processor, for interfacing the processor with the power sequence controller via the control signal line.
In the computer system, the processor may include means for, when all the devices connected to a specific input/output bus have been out of use for longer than a predetermined period of time, transmitting a command signal to stop the supply of power to the input/output bus to the power sequence controller via the interface circuit and the control signal line. In this case, the computer system may further comprise informing means for, whe n all the devices connected to the input/output bus have been out of use for longer than the predetermined period of time, notifying the processor of the fact.
The processor may include means for transmitting a command signal to stop the supply of power to the signal lines other than th e signal lines used to receive an interrupt notice from a device connected to the input/output bus and the signal lines used to receive a use-of-bus request notice from the device to the power sequence controller via the interface circuit and the control signal line, and means for, when receiving an interrupt notice or a use-of-bus request notice from the device connected to the input/output bus, transmitting a command signal to resume the supply of power to the power sequence controller via the interface circuit and the control signal line.
According to another aspect of the present invention, there is provided a computer system comprising: a processor containing at least one heavily power-consuming module including a floating point arithmetic module; and control means for controlling the supply and cut of power to the heavily power-consuming modules individually.
According to another aspect of the present invention, there is provided a computer system comprising: a processor containing at least one heavily power-consuming module including a floating point arithmetic module; and control means for controlling the supply and cut of a clock to the heavily power-consuming modules individually.
The computer system may further comprise a clock conversion device that is provided between an oscillation circuit and the heavily power-consuming module and is capable of converting the frequency of an inputted clock stepwise in the range from the original frequency to the stopping state in accordance with an inputted control signal. In this case, the control means may include means for, when the supply of the clock to the heavily power-consuming module is stopped, transmitting a control signal to the clock conversion device such that the frequency of the clock is converted stepwise in the direction of changing from the original frequency toward the stopping state, and when the supply of the clock to the heavily power-consuming module is resumed, transmitting a control signal to the clock conversion device such that the frequency of the clock is converted stepwise in the direction of changing from the stopping state toward the original frequency.
The computer system may further comprise sensing means for sensing the remaining capacity of a battery serving as a power supply. In this case, the control means may include means for adjusting the frequency of the clock supplied to the heavily power-consuming module in accordance with the remaining capacity of the battery sensed by the sensing means.
According to another aspect of the present invention, there is provided a computer system comprising: a power sequence controller for controlling the supply of power of a power source in accordance with an inputted control signal; at least one dynamic RAM chip; and a processor including means for, when the dynamic RAM chips have not been accessed for longer than a predetermined period of time, transmitting a command signal to stop the supply of power to the dynamic RAM chip to the power sequence controller.
The computer system may further comprise. informing means for, when the dynamic RAM chips have not been accessed for longer than the predetermined period of time, notifying the processor of the fact.
The computer system may further comprise relocation means for relocating the data items now in use scattered in the dynamic RAM chips so that they may be stored in the smallest number of dynamic RAM chips.
The computer system may further comprise determining means for determining whether or not the data items on the dynamic RAM chips have to remain stored. In this case, the processor may include means for, when receiving a notice from the informing means, transmitting a command signal to switch to the self-refreshing mode to the dynamic RAM chips that, in the determination of the determining means, have to continue storing the data, and transmitting to the power sequence controller a command signal to stop the supply of power to the dynamic RAM chips that, in the determination of the determining means, need not continue storing the data.
According to another aspect of the present invention, there is provided a computer system comprising: at least one dynamic RAM chip; and a processor for, when the dynamic RAM chips have not been accessed for longer than a predetermined period of time, transmi
Muratake Shigeki
Okazaki Yoshihiko
Omizo Takashi
Beausoleil Robert
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Phan Raymond N
LandOfFree
Computer system capable of controlling the power supplied to... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Computer system capable of controlling the power supplied to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Computer system capable of controlling the power supplied to... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2448933