Computer system and semiconductor device on one chip including a

Details Computer system and semiconductor device on one chip including a Computer system and semiconductor device on one chip including a

1997-05-02

2000-08-08

Gossage, Glenn

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

711163, 710108, 710200, 710240, G06F 1314, G06F 1342

Patent

active

061015849

ABSTRACT:
A central processing unit (CPU) having a built-in dynamic random-access memory (DRAM) with exclusive access to the DRAM when the CPU performs an interlock access to the DRAM. A memory controller prevents the DRAM from being externally accessed while the CPU is performing the interlock access. When the memory controller receives an external request for accessing the DRAM during a time when the CPU is performing an interlock access to the DRAM, the memory controller outputs a response signal indicating that external access to the DRAM is excluded or inhibited. The request signal can be a hold request signal for requesting a bus right or can be a chip select signal. The response signal can be a hold acknowledge signal or a data complete signal. The memory controller can be switched to and from first and second lock modes, where hold request and hold acknowledge signals are used during the first lock mode and chip select and data complete signals are used in the second lock mode.

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