Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
1999-01-11
2001-11-27
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S022000, C710S024000, C711S001000
Reexamination Certificate
active
06324599
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a computer system and, more particularly, to a direct memory access (“DMA”) controller which tracks DMA data transfers to a read-ahead buffer that is local to the computer system host processor without interrupting the processor.
2. Description of the Related Art
A time-consuming activity of a microprocessor entails moving blocks of memory from one subsystem within a computer system to another subsystem. The memory-moving chores can, in some instances, be handled by a DMA controller.
A DMA controller may include a specialized processor and numerous registers which keep track of the base location or source from which bytes of data are to be moved, the address or destination to where those bytes should be placed, and the number of bytes involved in the move operation. By noting the source, destination, and general operating parameters of the DMA transfer, the DMA controller allows direct communication from a peripheral device to main memory. The main memory is often denoted as “semiconductor” memory, which typically has a faster access time than devices connected to the peripheral bus (i.e., peripheral devices). The DMA controller provides communication with minimal involvement of the host processor.
The mechanism by which the DMA controller provides a channel between the peripheral device and the system memory occurs in accordance with a channel program or control blocks programmed within the system memory. Control blocks contain fields which are programmed with values that, when fetched by the DMA controller, instructs the DMA controller to transfer the desired data to or from main memory. In addition to a transfer control field, each control block may also include a field which points to a specific buffer that is typically arranged for the DMA controller. That buffer can then be used to receive data transferred from a peripheral device (or transferred from the system memory) depending on whether the DMA transfer operation is a read request or write request.
The control blocks are essentially storage locations within the system memory, and allocated by the device driver software. An important advantage in using control blocks is that one control block can point to a successive control block, and so forth to form a “chain” of control blocks. Therefore, each control block is used to control a single DMA transfer of data, and by linking numerous control blocks together in a chain, a sequence of DMA transfers can occur without host processor intervention. Thus, in addition to the transfer control field and the buffer pointer field, each control block may also have a pointer field directed to the next control block within the sequence. A description of control blocks, and control block chaining, is set forth in further detail within, for example, U.S. Pat. No. 5,251,312 (herein incorporated by reference).
The mechanism of chaining control blocks together can therefore be used to create a read-ahead buffer and allows many DMA transfers to occur without host processor intervention, provided the processor or the read requester is periodically informed of the whereabouts of that DMA transferred data. This implies that after data is transferred to a buffer via a control block, the address locations of the DMA transferred bytes be recorded in the read requester which will eventually call upon that data. Generally an interrupt signal is used to interrupt the host processor to inform the read requester that the buffer has reached a certain level of “fullness”. Since the read requester (e.g., processor, application program or operating system) now has information on the status of data bytes transferred from a specific address range of a peripheral (e.g., peripheral device address or device logic address) which sourced the DMA transfer, the read requester can then select that data from the buffer rather than the peripheral device if the read requested address matches with the addressed data stored within the buffer.
Placing data transferred from a slower peripheral device into a faster buffer during a DMA transfer proves beneficial if the data transferred is subsequently called upon by the read requester or host processor. For example, data can be transferred from a peripheral device according to a sequentially increasing and contiguous address space used by that device. That data is then sequentially placed into the buffer until the buffer is substantially full. When this occurs, it is important that the host processor be informed that data within a certain address range resides in a faster access, local buffer. Accordingly, any read requests issued by the processor to that address range can be quickly serviced by the buffer in lieu of the slower peripheral device.
Unfortunately, each time an interrupt is forwarded to the processor the current execution unit of the processor must be temporarily halted until after the interrupt has been serviced. Servicing each interrupt also incurs processor overhead. A somewhat high interrupt rate can further limit the overall performance of the host processor. Using an interrupt to denote the fullness of the buffer will, to some extent, counteract the benefits of using a read-ahead buffer in the first place. That is, a buffer which receives slower DMA transfers and stores the DMA transferred data in readiness for a read request from the processor will beneficially improve the access time to that data by the processor. However, if the processor is frequently undergoing interrupt, whatever gains provided by the read-ahead buffer will be limited by detriments caused by frequent interrupts.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by an improved DMA transfer technique which avoids interrupting the host processor at times when the read-ahead buffer (or “buffer”) is being filled. More specifically, the location and quantity of data transferred to the buffer hereof is kept track of within the control blocks rather than through use of an interrupt. Each byte transferred during a DMA cycle will increment a value within a byte count field of a corresponding control block. That value will be retained within one or more control blocks within a chain, and will be called upon later to indicate if a subsequent read request from the processor is to an address located within the buffer.
The chain of control blocks and associated byte count fields are contained within main memory. Each time a control block initiates a DMA transfer to the buffer, that control block will note the number of bytes transferred within its own byte count field. If multiple DMA transfers occur, then multiple byte count fields in respective control blocks are incremented with the appropriate number of bytes transferred. The byte counts of each control block can be added together to form a cumulative byte count number during times when a read request is issued. The read request will either be serviced from the buffer or from the peripheral device depending on whether the immediately preceding read request address (i.e., previous request address) plus the cumulative byte count encompasses the current request address. If so, it is noted that the entirety of data needed by the current request is contained within the buffer. If none of the requested data, or only a portion of the requested data, is within the buffer, then the requested data will be entirely drawn from the peripheral device.
The peripheral device contains bytes of data arranged in a sequentially increasing, logical (or block) address space. The read-ahead DMA transfer will occur between read request cycles and, more importantly, will begin at the conclusion of the previous read request address up through the byte count number at which the current read request occurs, until the buffer is full, or the device driver terminates the transfer. If the current read request address is within the previous ending address plus the byte count number, then it will be known that the current read request can be entirely serviced from the
Olson Steven E.
Zhou Ning
Conley & Rose & Tayon P.C.
Daffer Kevin L.
Du Ihuan
Lee Thomas
Oak Technology
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