Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1999-03-31
2003-07-29
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S124000, C711S141000, C711S121000, C711S130000
Reexamination Certificate
active
06601147
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to interconnected or clustered computer systems, and more particularly to a method of and system for maintaining an integrated shared-buffer memory in a system of interconnected or clustered computers, and still more particularly to a computer system in which shared-buffer memory is maintained in system random access memory (RAM).
2. Description of the Related Art
Systems that include multiple interconnected computers or processors have become fairly common. In such systems, the work of computing is divided between the computers or processors of the system. One example is a network or cluster in which one computer operates while another is in standby mode. The computer in standby mode can take over the work if the operating computer fails. Another example is a system of interconnected or clustered computers that performs large database searches. Each computer performs a different part of the search.
In interconnected or clustered systems, it is necessary that each computer have access to buffer memory that contains various system data. Typical existing solutions employ standard peripheral component interconnect (PCI) adapters with Input/Output (I/O)-based memory. These purely add on adapters require additional onboard RAM, thus increasing cost, and they suffer the performance degradation associated with I/O-based memory. It is an object of the present invention to provide an improved buffer memory system for interconnected or clustered computer systems.
The present invention provides a computer system with a shared-buffer memory. The computer system includes a plurality of interconnected host systems. Each of the host systems includes system random access memory, with a portion of the system random access memory being defined as shared-buffer memory. A system memory controller is operably connected to the system random access memory to determine, among other things, if the host has updated the shared-buffer memory, and if so, to signal that the shared-buffer memory has been updated. A buffer control and interconnect device is operably connected to the system memory controller. In response to a signal from the system memory controller that the shared-buffer memory has been updated, the buffer control and interconnect device reads the update from the shared-buffer memory and exports the update. The exported update is received at the buffer control and interconnect device of each of the other host systems. The receiving buffer control and interconnect device writes the update to its shared-buffer memory.
REFERENCES:
patent: 3771137 (1973-11-01), Barner et al.
patent: 5815167 (1998-09-01), Muthal et al.
patent: 5872998 (1999-02-01), Chee
patent: 6038642 (2000-03-01), Arimilli et al.
patent: 6092157 (2000-07-01), Suzuki
patent: 6115761 (2000-09-01), Daniel et al.
Bealkowski Richard
Bland Patrick Maurice
Bracewell&Patterson,LLP
Gossage Glenn
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