Computer system and method for fetching, decoding and...

Electrical computers and digital processing systems: processing – Processing control – Branching

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C712S207000, C712S237000

Reexamination Certificate

active

07047399

ABSTRACT:
A computer system for executing branch instructions and a method of executing branch instructions are described. Two instruction fetchers respectively fetch a sequence of instructions from memory for execution and a sequence of instructions commencing from a target location identified by a set branch instruction in a sequence of instructions being executed. When an effect branch signal is generated, the target instructions are next executed, and the fetcher which was fetching the instructions for execution commences fetching of the target instructions.The effect branch signal is generated separately from the set branch instruction.In another aspect, the effect branch signal is generated on execution of a conditional effect branch instruction, located at the point in the instruction sequence where the branch is to be taken.

REFERENCES:
patent: 3426330 (1969-02-01), Marx et al.
patent: 3551895 (1970-12-01), Driscoll, Jr.
patent: 3573854 (1971-04-01), Watson et al.
patent: 3577189 (1971-05-01), Cocke et al.
patent: 4742451 (1988-05-01), Bruckert et al.
patent: 4974155 (1990-11-01), Dulong et al.
patent: 5615386 (1997-03-01), Amerson et al.
patent: 5961637 (1999-10-01), Sturges et al.
patent: A-0 355 069 (1990-02-01), None
patent: A-0 219 203 (1995-02-01), None
Hamacher, V. Carl, Vranesic, Zvonko G., Zaky, Safwat G., Computer Organization, 2ndedition, McGraw-Hill Book Company, 1984, pp. 22.
European Search Report from United Kingdom Patent Application No. 9412487.2, filed Jun. 22, 1994.
International Journal Of Mini And Microcomputers, vol. 11, No. 1, 1989, Calgary, California US, pp 13-17. Cortadella and Llaberia “Making Branches Transparent To the Execution Unit”.
Proceedings 4th MIT Conference: Advanced Research In VLSI, Apr. 7, 1986, Cambridge, MA, US pp 73-88, Plaszkun and Farrens “An Instruction Cache Designs For Use With a Delayed Branch”.
IBM Technical Disclosure Bulletin, vol. 14, No. 2, May 1972, New York, US, pp 3599-3611, Beebe et al, “Instruction Sequencing Control”.
Computer Architecture: A Quantitative Approach, David A. Patterson, et al., pp. 265-270 (Chapter 6, Sectopm 4), no date provided.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Computer system and method for fetching, decoding and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Computer system and method for fetching, decoding and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Computer system and method for fetching, decoding and... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3552828

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.