Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1995-02-21
2001-07-31
Beausoleil, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S053000
Reexamination Certificate
active
06269458
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a computer system and method for a computer diagnostic. More particularly, the present invention relates to a computer system and method for diagnosing and isolating faults in multiple card computer systems.
Typical computer systems use diagnostics to verify proper operation and addressing of internal memory devices. Conventional diagnostics involve well-known diagnostic techniques in which the processor writes data to and reads data from memory. In the most basic implementation, the processor simply writes a pattern of data to a particular memory location and then reads back the data from that location, verifying its value. This procedure is then repeated for different patterns and different memory locations. More complex techniques test differently. For example, one technique writes high bits to an entire memory device, writes low bits to a single location within that memory device, and reads all locations of the memory device to verify that the data write to the single location has not corrupted other memory locations. Other techniques, some including statistical analyses, are well known in the art.
The techniques also work in shared-bus computer systems in which a processor is connected to external cards or devices (e.g., direct memory access (DMA) agents, storage devices, input/output (I/O) ports, communication devices, and other types of separate processors and external cards) via an external bus. The processor writes data to a memory location on an external card via the external bus and then reads back the data from that location, verifying its value.
This technique has a shortcoming, however. If it detects a fault, the technique cannot isolate the failing component. For example, if a processor fails to access a memory location on an external card, either the processor card, the card containing the memory location, or the external bus itself may have failed. To repair the system, a technician must analyze multiple components to find the faulty device. Accordingly, diagnostics capable of fault isolation are highly desirable to facilitate repairs and card replacements, especially in complex environments with numerous external cards. Examples of such environments include conventional and cellular telephony switching systems.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a computer system and method for diagnosing and isolating faults that substantially obviates one or more of the problems due to limitations and disadvantages of the prior art.
It is an object of the present invention to provide a computer system and method for efficiently diagnosing and isolating faults in a multiprocessor system.
It is a further object of the present invention to provide a computer system and method for efficiently diagnosing and isolating faults in a modular computer system.
It is another object of the present invention to provide a computer system and method facilitating fast and inexpensive repairs and enhancing reliability in telephony switching systems.
It is yet another object of the present invention to provide a computer system and method facilitating self-diagnosis of an external bus interface of a processor card up to the back connector connected to the external bus.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements, method steps, and combinations particularly pointed out in the appended claims.
To achieve the objects and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention comprises a method for diagnosing and isolating faults in a computer system comprising a bus coupled to a processor, a register, a diagnostic state machine, and a memory. The diagnostic state machine is associated with a first address space and the memory is associated with a second address space. The method includes the steps of writing, from the processor using the bus, a first value to a first address within the first address space and latching this first value in the register using the diagnostic state machine. The method further includes the steps of writing the first value to a second address within the second address space and reading a second value from the memory, by the processor over the bus, at the second address. The second value is compared to the first value to indicate an error if they are different.
Furthermore, as embodied and broadly described herein, the invention comprises a computer system for diagnosing and isolating faults. The computer system includes a bus coupled to a processor, a register, a diagnostic state machine, and a memory. The diagnostic state machine is associated with a first address space and the memory is associated with a second address space. The second address space is related to the first address space such that locations in the first address space correspond with locations in the second address space. The system further includes means for writing a first value to a first address within the first address space and means for writing the first value to a second address within the second address space where the second address is associated with the first address in the first address space.
Both the foregoing general description and the following detailed description are exemplary and explanatory only, and are not restrictive of the invention, as claimed.
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Jeter Jay D.
Landry Ronald J.
Baderman Scott T.
Beausoleil Robert
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Nortel Networks Limited
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