Computer system and control method for controlling processor...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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C711S130000, C711S141000, C711S204000, C711S213000, C712S207000

Reexamination Certificate

active

07895399

ABSTRACT:
A processor reads a program including a prefetch command and a load command and data from a main memory, and executes the program. The processor includes: a processor core that executes the program; a L2 cache that stores data on the main memory for each predetermined unit of data storage; and a prefetch unit that pre-reads the data into the L2 cache from the main memory on the basis of a request for prefetch from the processor core. The prefetch unit includes: a L2 cache management table including an area in which a storage state is held for each position in the unit of data storage of the L2 cache and an area in which a request for prefetch is reserved; and a prefetch control unit that instructs, the L2 cache to perform the request for prefetch reserved or the request for prefetch from the processor core.

REFERENCES:
patent: 7039766 (2006-05-01), Smith
patent: 2005/0102477 (2005-05-01), Sukegawa
patent: 2006/0004966 (2006-01-01), Maeda et al.
patent: 2006/0020758 (2006-01-01), Wheeler et al.
patent: 2006/0112229 (2006-05-01), Moat et al.
patent: 2005-242527 (2004-02-01), None
patent: 2006-18474 (2004-06-01), None
U.S. Appl. No. 11/357,972, Tomita et al.
U.S. Appl. No. 11/358,052, Aoki et al.

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