Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-07-30
2002-10-15
Baderman, Scott (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C711S114000
Reexamination Certificate
active
06467047
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to computer storage systems and, more particularly, to high performance controllers for disk array systems. The controllers incorporate a control store memory with primary and secondary data and parity areas for high reliability.
BACKGROUND OF THE INVENTION
Computer storage systems for high capacity, on-line applications are well known. Such systems use arrays of disk devices to provide a large storage capacity. To alleviate the delays inherent in accessing information in the disk array, a large capacity system cache memory is typically utilized. Controllers known as back end directors or disk adaptors control transfer of data from the system cache memory to the disk array and from the disk array to the system cache memory. Each back end director may control several disk devices, each typically comprising a hard disk drive. Controllers known as front end directors or host adaptors control transfer of data from the system cache memory to a host computer and from the host computer to the system cache memory. A system may include one or more front end directors and one or more back end directors.
The front end directors and the back end directors perform all functions associated with transfer of data between the host computer and the system cache memory and between the system cache memory and the disk array. The directors control cache read operations and execute replacement algorithms for replacing cache data in the event of a cache miss. The directors control writing of data from the cache to the disk array and may execute a prefetch algorithm for transferring data from the disk devices to the system cache memory in response to sequential data access patterns. The directors also execute diagnostic and maintenance routines. In general, the directors incorporate a high degree of intelligence.
Current computer storage systems are characterized by high performance and high reliability. Nonetheless, as the performance of the host computers which operate with the computer storage systems increases, it is necessary to provide computer storage systems having enhanced performance. In particular, operating speeds must be increased as the operating speeds of host computers increase. Furthermore, as the cost of computer memory decreases and program complexity increases, the volumes of data transferred increase. Because computer storage systems are frequently used in highly critical applications, reliability is an important consideration. The storage systems must remain operational, even when certain components and subsystems fail. Accordingly, the storage systems may incorporate redundant hardware and are extensively tested. Because the performance of computer storage systems is determined to a significant degree by the performance of the controllers, there is a need for very high performance, high reliability controllers for computer storage systems.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, computer apparatus comprises a processor, a memory that is accessible by the processor and a memory controller for controlling writing to and reading from the memory in response to requests from the processor. The memory comprises a primary data area, a primary parity area, a secondary data area and a secondary parity area. The memory controller comprises means for writing data words in both the primary data area and the secondary data area and for writing parity words in corresponding locations in both the primary parity area and the secondary parity area, means responsive to a read request from the processor for accessing a requested data word in the primary data area and accessing the corresponding parity word in the primary parity area, means for checking the parity of the requested data word, means responsive to good parity of the requested data word for supplying the requested data word to the processor, and means responsive to a primary parity error in the requested data word for accessing the requested data word in the secondary data area and accessing the corresponding parity word in the secondary parity area. The requested data word from the secondary data area is supplied to the processor in the absence of a secondary parity error.
The memory controller may further comprise means for checking the parity of the requested data word from the secondary data area, means responsive to good parity of the requested data word from the secondary data area for supplying the requested data word to the processor, and means responsive to a secondary parity error of the requested data word from the secondary data area for generating an exception that is indicative of a memory error. The memory controller may further include means responsive to a primary parity error for setting one or more status bits indicative of the primary parity error. The memory controller may generate an exception only if a secondary parity error occurs when the requested data word is accessed in the secondary data area. In another feature, the memory controller may further comprise means for writing data words in one of the primary data area and the secondary data area and for writing parity words in corresponding locations in one of the primary parity area and the secondary parity area.
According to a second aspect of the invention, a controller is provided for a computer storage system comprising an array of storage devices, a system cache memory, and a plurality of controllers for controlling data transfer to and between the array of storage devices, the system cache memory and a host computer. The controller comprises a processor, a memory and a memory controller as described above.
According to a third aspect of the invention, a method is provided for controlling writing to and reading from memory in response to requests by a processor. The method comprises the steps of organizing the memory to include a primary data area, a primary parity area, a secondary data area, and a secondary parity area, writing data words in both the primary data area and the secondary data area and writing parity words in corresponding locations in both the primary parity area, and the secondary parity area. In response to a read request from the processor, a requested data word is accessed in the primary data area, and the corresponding parity word is accessed in the primary parity area. The parity of the requested data word is checked, and the requested data word is supplied to the processor in response to good parity of the requested data word. In the event of a primary parity error of the requested data word, the requested data word is accessed in the secondary data area, and the corresponding parity word is accessed in the secondary parity area.
The parity of the requested data word from the secondary data area is checked, and the requested data word is supplied to the processor in response to good parity of the requested data word from the secondary data area. An exception that is indicative of a memory error is generated in response to a secondary parity error of the requested data word from the secondary data area.
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Bauer Rudy M.
Scaringella Stephen L.
Tung Victor W.
Baderman Scott
Chu Gabriel
EMC Corporation
Wolf Greenfield & Sacks P.C.
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