Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-09-15
2003-08-26
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S106000, C710S104000, C710S105000, C710S116000, C710S305000
Reexamination Certificate
active
06611891
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to computer systems and more particularly to a configuration of computer system having a high speed communication link having multiple pipes operating on the communication link.
2. Description of the Related Art
Traditional personal computer architectures partition the computer system into the various blocks shown in the exemplary prior art system illustrated in FIG.
1
. One central feature of this prior art architecture is the use of the Peripheral Component Interface (PCI) bus
101
as the connection between the “north bridge” integrated circuit
103
and the “south bridge” integrated circuit
105
. The north bridge functions generally as a switch connecting CPU
107
, a graphics bus
109
such as the Advanced Graphics Port (AGP) bus, the PCI bus and main memory
111
. The north bridge also contains the memory controller function.
The south bridge generally provides the interface to the input/output (I/O) portion of the system with the possible exception of video output as illustrated in FIG.
1
. Specifically, the south bridge
105
provides a bridge between the PCI bus and legacy PC-AT (Advanced Technology) logic. The south bridge also provides a bridge to the legacy ISA bus
115
, the Integrated Device Electronics (IDE) disk interface
117
and the Universal Serial Bus (USB)
119
. In the illustrated prior art architecture, PCI bus
101
also functions as the major input/output bus for add-in functions such as network connection
121
. The various busses and devices shown in
FIG. 1
are conventional in the personal computer industry and are not described further herein unless necessary for an understanding of the present invention.
In current and future personal computer systems, two basic types of data are transferred between integrated circuits: isochronous data and asynchronous data. Isochronous data refers to data used in real-time data streams such as audio data or motion-picture video data. Asynchronous data is used for all other transfers, such as central processing unit (CPU) accesses to memory and peripherals or bulk data transmissions from a hard drive into system memory.
The PCI bus causes a lack of determinism in the system because any function on the PCI bus can become master of the bus and tie up the bus. Thus, the throughput available on the PCI bus for a particular transfer and the latency that is involved for that transfer is unknown. PCI bus load fluctuations can result in uncertain and irregular quality of service. Therefore, having a PCI bus as the major input/output bus means that the major input/output bus of present day computer systems does not provide proper support for both isochronous and asynchronous data. If a computer system gives asynchronous data priority or treats isochronous data as asynchronous data, then those functions relying on real time data, such as motion-picture video, may not function satisfactorily. Alternatively, if a computer system prioritizes isochronous data, then the performance of the computer system can suffer since the latency of asynchronous data may become unacceptably long. As computer systems are called on to perform more and more real time activity, such as real time video, it becomes more critical that asynchronous and isochronous data be treated in a manner that prevents problems from occurring in the real time tasks without adversely effecting other aspects of computer performance.
In addition, as the number of functions integrated onto the integrated circuits of computer systems increases, the need for additional integrated circuit package pins also increases. Supporting the host bus, the memory interface, the PCI bus and a graphics interface results in a north bridge integrated circuit having a relatively large number of pins that is relatively unpopulated in terms of the number of transistors on the integrated circuit. The large number of pins requires the integrated circuit to be larger than would otherwise be necessary and therefore increases costs.
It would be desirable therefore, to have a high speed major interconnect bus providing improved quality of service for both isochronous and asynchronous traffic classes. It would also be desirable to reduce the pressure for additional pins on the integrated circuits making up the computer system.
SUMMARY OF THE INVENTION
One aspect of providing a high speed interconnect is to configure the resources in the computer system necessary to support a high speed interconnect. In one embodiment of the invention, a method is provided for configuring resources in a computer system that includes a central processing unit (CPU). The resources to be configured include first and second control circuits in respective first and second integrated circuits which are connected by a communication link transferring data over a plurality of pipes. According to the method, a link bridge includes upstream configuration registers within the first control circuit located closest to the CPU and downstream configuration registers within the second control circuit located farthest from the CPU. A link header initializes the link bridge, the link header including upstream data for the first control circuit and down stream data for the second control circuit.
The method may also include configuring the width of the communication link. In that aspect, configuring the link bridge includes accessing an upstream link width register. The upstream link width register includes a receive width field, a transmit width field, a maximum receive width field and a maximum transmit width field. The maximum receive and transmit fields in the upstream link width register specify the physical size of transmit and receive data portions, respectively, for the upstream side of the link. In addition, configuration includes accessing a downstream link width register that includes a downstream receive width field, a downstream transmit width field, a downstream maximum receive width field and a downstream maximum transmit width field. The downstream maximum receive and transmit fields specify the physical size of transmit and receive data portions for the downstream side of the link. The configuration mechanism, e.g. configuration software, sets the upstream receive width field to be the smaller of the upstream maximum receive width field and the downstream maximum transmit width field and sets the upstream transmit width field to be the smaller of the upstream maximum transmit width field and the downstream maximum receive width field. In addition, configuration software sets the downstream receive width field to be the smaller of the upstream maximum transmit width field and the downstream maximum receive width field and sets the downstream transmit width field to be the smaller of the upstream maximum receive width field and the downstream maximum transmit width field. In that way, the transmit and receive widths for the link are specified.
Another embodiment provides a computer system that includes a first integrated circuit and a communication link connected to the first integrated circuit. The first integrated circuit contains first configuration registers for configuring first control logic for the communication link in the first integrated circuit. The communication link connects a second integrated circuit to the first integrated circuit. The communication link carries transactions between the first and second integrated circuit over a plurality of logical pipes or channels. The second integrated circuit contains a plurality of second configuration registers for configuring second control logic for the communication link. The first and second configuration registers are located in a uniquely identified bridge configuration address space. In one embodiment the bridge configuration address space is identified by a unique combination of bus number, device number and function number.
REFERENCES:
patent: 4464772 (1984-08-01), Buckley et al.
patent: 4858116 (1989-08-01), Gillett, Jr. et al.
patent: 4941083 (1990-07-01), Gillett, Jr
Gulick Dale E.
Hewitt Larry D.
Advanced Micro Devices , Inc.
King Justin
Ray Gopal C.
Zagorin, O'Brien & Graham
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