Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-11-26
2008-11-25
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07458048
ABSTRACT:
A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intended to have a same logical function. A plurality of testcase types are then created by constraining one or more internal signals, and one or more test scripts representing the plurality of testcase types are produced. The method also includes verifying the second digital design with a testing simulation program by comparing results of the test scripts from the operational model and the reference model.
REFERENCES:
patent: 5892947 (1999-04-01), DeLong et al.
Chen, Y.A. & Bryant R. “Computer Aided Verification”, Conference, Jun. 2-Jul. 2, 1998, 8 pp., vol. 1427, ISBN 3-540-64608-6, USA.
Baumgartner Jason Raymond
Jacobi Christian
Paruthi Viresh
Weber Kai Oliver
Chiang Jack
Dillon & Yudell LLP
Doan Nghia M
International Business Machines - Corporation
Salys Casimer K.
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