Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
1999-02-19
2002-02-05
Shin, Christopher B. (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S040000, C710S107000, C710S124000, C710S120000, C710S244000, C709S232000
Reexamination Certificate
active
06345326
ABSTRACT:
FIELD OF INVENTION
The subject of the present invention in general pertains to a new Input-Output facility design that exploits high bandwidth integrated network adapters.
BACKGROUND OF THE INVENTION
In a network computing environment, multitudes of commands and requests for retrieval and storage of data are processed every second. To properly address the complexity of routing these commands and requests, environments with servers have traditionally offered integrated network connectivity to allow direct attachments of clients such as Local Area Networks (LANs). Given the size of most servers, the number of clients usually is in the range of hundreds to thousands and the bandwidth required in the 10-100 Mbits/sec range. However, in recent years the servers have grown and the amount of data they are required to handle has grown with them. As a result, the existing I/O architectures need to be modified to support this order of magnitude increase in the bandwidth.
In addition, new Internet applications have increased the demand for improved latency. The adapters must support a larger number of users and connections to consolidate the network interfaces which are visible externally. The combination of all the above requirements presents a unique challenge to server I/O subsystems.
Furthermore, in large environments such as International Business Machines Enterprise System Architecture/390 (Enterprise System Architecture/390 is a registered trademark of International Business Machines Corporation), there are additional requirements that the I/O subsystem must remain consistent with existing support. Applications must continue to run unmodified, and error recovery and dynamic configuration must be preserved or even improved. Sharing of I/O resources must be enabled as well as the integrity of the data being sent or received. This presents new and complex challenges that need to be resolved.
In order to achieve bandwidths which are dramatically higher and still achieve other required challenges, a new system architecture is needed.
SUMMARY OF THE INVENTION
A computer program device and product is provided for timely processing of data. The computer program device comprises a computer program storage device readable by a digital processing apparatus and a program means on the program storage device and including instructions executable by the digital processing apparatus for ensuring that all queues in a queuing mechanism residing on said program storage device remain active and that any data in the queues is being timely processed by: designating at least one set of queues in the queuing mechanism as input queues and another as output queues; issuing a signal adapter instruction to provide initiative to check content of any or all queues in the queuing mechanism; specifying initiate-output or initiate-input appropriately by means of said signal adapter instruction to cause associated adapter to asynchronously process said output or input queues; and causing synchronization by means of said signal adapter instruction by signaling the associated data queues to update all entries in order to render them current.
The computer program product is for use with a computer system and has a main storage in processing communication with an interface element having adapters for storing a queuing mechanism storing data. It comprises of a data storage device including a computer usable medium having computer readable program means for ensuring proper and timely processing of data and computer usable code means for dedicating at least one set of queues of the queuing mechanism as input queues and another set as output queues. In addition it includes computer readable code means for generating a signal adapter instruction designated to provide initiative to check content of any or all queues in said queuing mechanism.
REFERENCES:
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patent: 5659794 (1997-08-01), Caldarale et al.
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Baskey Michael E.
Brice Frank W.
Casper Daniel F.
Easton Janet R.
Glassen Steven G.
Gonzalez Floyd A.
Neff Lily
Shin Christopher B.
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