Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent
1997-12-15
2000-05-23
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
711151, 711150, G06F 100, G06F 1200
Patent
active
06067606&
ABSTRACT:
A computer processor includes a dynamic latency module. The dynamic latency module includes a read-only memory ("ROM") in which is stored a plurality of sets of latency values. The dynamic latency module further includes a register coupled to the ROM and adapted to store at least one set of the plurality of sets of latency values. The dynamic latency module dynamically sets a plurality of memory access latency values by determining an operating speed of the processor and implementing one of the plurality of sets of latency values based on the operating speed.
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Holscher Brian
Jones Jeffrey R.
Wilson, Jr. James A.
Chan Eddie P.
Intel Corporation
Williams, II Jan S.
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