Computer memory subsystem and method for performing opportunisti

Details Computer memory subsystem and method for performing opportunisti Computer memory subsystem and method for performing opportunisti

1996-12-16

1999-05-11

Gossage, Glenn

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711105, 711106, 711169, 365233, 36518904, 365193, G06F13/00

Patent

active

059039167

ABSTRACT:
A computer memory subsystem and associated method are disclosed in which memory transaction latency and bandwidth in the memory subsystem are improved through the opportunistic transfer of write data from a data path to a memory buffer coupled to a targeted memory bank during an access latency period within a non-memory write operation, such as, e.g., a read or refresh operation. The opportunistic write data transfer operation utilizes otherwise unused memory data bus cycles within a read or refresh operation for performance of the write data transfer, without adding clock cycles to the read or refresh operation. Because the write data is transferred to the memory buffer coupled to the memory bank during the latency period of the memory operation preceding the write operation, the total turnaround time for, e.g., performing a read operation followed by a write operation is reduced.

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patent: 5623447 (1997-04-01), Shimoda
patent: 5655105 (1997-08-01), McLaury

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