Computer memory interface having a memory controller that automa

Details Computer memory interface having a memory controller that automa Computer memory interface having a memory controller that automa

1999-03-30

2000-10-24

Nelms, David

Static information storage and retrieval

Read/write circuit

Signals

365201, 36523008, G11C 700

Patent

active

061377341

ABSTRACT:
A memory controller features programmable delay buffers that allow the memory interface signals to be automatically adjusted. By fine tuning the delay values, the memory controller can compensate for impedance characteristics that affect the memory interface timing. The memory controller includes a built-in self test mode, in which it runs a series of memory tests using a plurality of different delay combinations for the delay buffers. After running the built-in self test, the memory controller programs the delay buffers to values which allow the memory transactions to occur without errors, ensuring optimal memory interface timing.

REFERENCES:
patent: 4991169 (1991-02-01), Davis et al.
patent: 5530874 (1996-06-01), Emery et al.
patent: 5732094 (1998-03-01), Petersen et al.

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