Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2000-05-02
2003-04-22
Elmore, Reba I. (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S157000, C711S173000, C711S202000, C711S211000
Reexamination Certificate
active
06553478
ABSTRACT:
The invention relates to circuits and methods for accessing computer memory using X and Y memory addressing as well as interleaved memory addressing.
BACKGROUND OF THE INVENTION
Computer memories are known in which the memory space available is mapped to provide separately addressable regions each of which may be provided by a plurality of memory banks. In the case of an interleaved memory system, data may be located in each of the banks using a common addressing system so that data is located in a new bank address only when each of the bank storage locations has been used for the preceding address. In an X-Y organisation, some of the memory banks form a Y memory region while other memory banks form an X memory region and the two regions are located at different mapped positions within the memory space. In this way, the storage location in the X bank are addressed quite independently of the storage locations within the Y bank.
In some applications, an interleaved organisation of the memory addressing may enable compilers to be more efficient in generating high performance code. On the other hand, some digital signal processing (DSP) applications require an X-Y organisation for specific algorithms.
It is an object of the present invention to provide a computer system in which both types of memory addressing can be employed.
SUMMARY OF THE INVENTION
The invention provides memory circuitry for a computer system having a plurality of memory banks forming at least part of the mapped memory space, a first part of said space providing an interleaved memory region formed by each of said memory banks so that data is stored in each of the banks within the interleaved region, a second part of said space providing an X memory region using only one or some of said memory banks and a third part of said space providing a Y memory region using the or each memory bank not used in the X memory region, each of said interleaved, X and Y memory regions being separately mapped within the memory space, together with circuitry to generate an access address and an indication of whether the access is an interleaved access or an X or Y access, said access address including a most significant set of bits which indicate which of the interleaved, X or Y memory regions is to be accessed, and a least significant set of bits which include an indication of an address within a bank of the accessed region, at least one bit within said least significant set selecting one bank within an accessed region if that region has more than one bank and one bit in said most significant set of bits indicating selectively the X or the Y memory region during an X or Y access, and memory access circuitry arranged to selectively access the memory in response to said access address.
Preferably at least four memory banks are provided, said interleaved region being provided in part by all of said banks, said X region being provided by part of half of said banks, and said Y region being provided by part of the remainder of said banks not used by the X region.
Preferably each of said X and Y regions have two memory banks and each of said interleaved, X and Y regions has a different mapping address within the memory space indicated by some bits in the most significant part of a memory access address.
In one embodiment two of the least significant bits of an access address are used by the memory access circuitry in an interleaved access to identify the memory bank being accessed.
Preferably one of the least significant set of bits of the memory access address is used together with one of the most significant set of bits of the access address to determine which bank is to be accessed during an X or Y access.
Preferably the set of least significant bits includes a set of bank addressing bits of immediately greater significance than the bits forming the bank selection, said bank addressing bits providing an address within the selected bank.
Conveniently said memory access circuitry includes a plurality of multiplexing circuits, one multiplexing circuit selecting from an access address one or more bits to determine which bank is to be accessed and a second multiplexing circuit for selecting other bits from an access address to determine an address within the selected bank.
The invention also provides a method of accessing memory in a computer system comprising defining a plurality of memory banks forming at least part of a map memory space, a first part of said space providing an interleaved memory region formed by each of said memory banks so that data is stored in each of the banks within the interleaved region, a second part of said space providing an X memory region using only one or some of said memory banks, and a third part of said space providing a Y memory region using the or each memory bank not used in the X memory region, each of said interleaved, X and Y memory regions being separately mapped within the memory space, said method further comprising generating a access address including a most significant set of bits which indicates which of the interleaved, X or Y memory regions is to be accessed, and a least significant bit or bits which include an indication of an address within a bank of an accessed region, at least one of said least significant set of bits selecting one bank within an accessed region if that region has more than one bank, and one of said most significant set of bits indicating selectively the X or Y memory region during an X or Y access, and accessing selectively the memory in response to said access address.
Preferably two memory banks are provided for each of said X and Y memory regions and four memory banks are provided for the interleaved memory region, the least significant two bits of the memory address being used to select a bank in an interleaved memory access and the least significant bit being used together with one bit of the most significant set of bits to determine a memory bank during an X or Y memory access.
In one embodiment the bits used to indicate an address within a bank have a bit of greater significance during an interleaved access than the bits used to provide a bank address during an X or Y access, thereby providing a larger range of addresses within a bank during an interleaved access than the range of addresses available during an X or Y access.
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Elmore Reba I.
Morris James H.
Skrivanek, Jr. Robert A.
STMicroelectronics S.A.
Wolf Greenfield & Sacks P.C.
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