Computer logic simulation with dynamic modeling

Details Computer logic simulation with dynamic modeling Computer logic simulation with dynamic modeling

1992-10-29

1995-12-19

Voeltz, Emanuel T.

Boots, shoes, and leggings

364489, 395920, G06F 1560

Patent

active

054774748

ABSTRACT:
A method for improving the performance of a computer logic simulator in a computer system in which the operation of a logic design is simulated by converting a network list representative of the logic design into a simulator netlist and applying predetermined input vectors to the simulator netlist representative of the logic design in order to generate output vectors representative of the response of the simulator netlist. Portions of the network list are converted to dynamic device models in the form of executable code, which is assembled in a dynamic device model file. The remaining portions of the network list are converted to a simulator netlist, which is stored in a simulator netlist file. Both the dynamic device models and the simulator netlist are used to perform the simulation process. Since the dynamic device models are in the form of executable code, which can be directly read during the simulation process, the speed of operation of the simulation process is substantially increased, with a corresponding reduction in the total processing time required. In addition, the size of the simulator netlist is substantially reduced.

REFERENCES:
patent: 4527249 (1985-07-01), Van Brunt
patent: 4831543 (1989-05-01), Mastellone
patent: 4922445 (1990-05-01), Mizoue et al.
patent: 4937770 (1990-06-01), Samuels et al.
patent: 4939681 (1990-07-01), Yokomizo et al.
patent: 5084824 (1992-01-01), Lam et al.
patent: 5105373 (1992-04-01), Rumsey et al.
patent: 5163016 (1992-11-01), Har'El et al.
patent: 5220512 (1993-06-01), Watkins et al.
patent: 5258932 (1993-11-01), Matsuzaki
patent: 5278769 (1994-01-01), Bair et al.
patent: 5297066 (1994-03-01), Mayes
patent: 5301318 (1994-04-01), Mittal
patent: 5351197 (1994-09-01), Upton et al.
J. D. Calhoun et al, "A Framework and Method for Hierarchical Test Generation", IEEE 1989 International Test Conference, paper 21.3, pp. 480-489.
G. Lakhani et al, "Partition Based Heuristics for Gate Matrix Layout", IEEE 1989 International Symposium on Circuits and Systems, pp. 897-900, vol. 2.
Pedram et al, "Interconnection Length Estimation for Optimized Standard Cell Layouts", IEEE 1989 International Conference on Computer-Aided Design, pp. 390--393.
Singh et al, "From Logic to Symbolic Layout for Gate Matrix", IEEE Trans. on CAD of Int. Circuits and Systems 1992, vol. 11, Iss. 2. pp. 216-227.

Affiliated with

Also associated with

Rating

Computer logic simulation with dynamic modeling does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Computer logic simulation with dynamic modeling, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Computer logic simulation with dynamic modeling will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-996777