Computer including data signal monitoring circuit

Details Computer including data signal monitoring circuit Computer including data signal monitoring circuit

1998-05-29

2000-03-07

Thai, Xuan M.

Electrical computers and digital data processing systems: input/

Intrasystem connection

710129, 710 16, G06F 1300

Patent

active

060353538

ABSTRACT:
In a system having a processor, a memory and a peripheral circuit which communicate via a common bus, a signal detector and a compression circuit are included to facilitate data monitoring by a logic simulator. The signal detector is also connected to the common bus. In monitoring a target circuit, the signal detector decodes an address of a bus signal to determine if the signal is input to/output from the target circuit. The signal detector applies mask data, stored in a mask memory, to the bus signal, except for the bus data input to/output from the target signal, to generate a masked signal. The masked signal is then compressed using the compression circuit. The data input to/output from the target circuit and the compressed, masked signal are then stored in a memory of the logic simulator. Masking and compressing the bus signals reduces the amount of data stored by the logic simulator.

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