Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-08-13
2004-07-27
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06769111
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a computer-implemented method of process analysis for analyzing the degree of achievement of a predetermined effect exhibited by one predetermined process included in an entire manufacturing operation.
2. Description of the Background Art
In general, products such as semiconductor devices including a DRAM, a microcomputer and the like are manufactured through a manufacturing operation including a plurality of processes. Conventionally, in order to find product yield of such products, an overall electrical characteristic quality test has been performed on each of the products as completed after the manufacturing operation.
To simply find product yield in the conventional manner as noted above, however, could hardly allow for accurate analysis of the degree of achievement of a predetermined effect, which is represented by the quality of each product, for example, exhibited by one predetermined process in the manufacturing operation including a plurality of processes.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a computer-implemented method of process analysis which makes it possible to accurately analyze the degree of achievement of a predetermined effect exhibited by one predetermined process included in an entire manufacturing operation including a plurality of processes.
According to the present invention, a computer-implemented method of process analysis includes the following steps (a) to (e). The step (a) is to perform a first manufacturing operation including a predetermined process to obtain a first number of products. The step (b) is to perform a second manufacturing operation differing from the first manufacturing operation only in details associated with the predetermined process to obtain a second number of products of the same kind as those obtained by the step (a). The step (c) is to determine whether or not a predetermined effect is achieved with respect to each of the products obtained by the steps (a) and (b). The step (d) is to classify the products obtained by the steps (a) and (b) into four categories depending on which of the first manufacturing operation and the second manufacturing operation has been performed, and on whether or not the predetermined effect has been achieved. The step (e) is to analyze a degree of achievement of the predetermined effect exhibited by the predetermined process based on classification of the step (d), to provide an analysis result.
The classification of the products into four categories depending on which of the first and second manufacturing operations has been performed and whether or not the predetermined effect has been achieved can be used as classification data. By using the classification data, it is possible to obtain an accurate result of analyzing the degree of achievement of the predetermined effect which takes into consideration difference between the first manufacturing operation including the predetermined process and the second manufacturing operation differing from the first manufacturing operation only in details associated with the predetermined process.
This and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4885712 (1989-12-01), Yamane
patent: 6070131 (2000-05-01), Damon et al.
patent: 6256593 (2001-07-01), Damon et al.
patent: 6341241 (2002-01-01), Mugibayashi et al.
patent: 6456951 (2002-09-01), Maeda et al.
patent: 6473665 (2002-10-01), Mugibayashi et al.
patent: 6601192 (2003-07-01), Bowman-Amuah
patent: 2002/0095645 (2002-07-01), Rodeh
Pak, J. et al., “Advanced methods for analysis of wafer-to-wafer yield variation”, Advanced Semiconductor Manufacturing Conference and Workshop, IEEE /SEMI, Sep. 10-12, 1997, pp 62-66.*
Lee, F.;“Advanced yield enhancement: integrated yield analysis”, Advanced Semiconductor Manufacturing Conference and Workshop, 1997. IEEE /SEMI , Sep. 10-12, 1997 pp.: 67-75.*
Rajkanan, K.; “Yield analysis methodology for low defectivity wafer fabs”, Memory Technology, Design and Testing, 2000. Records of the 2000 IEEE International Workshop on , Aug. 7-8, 2000 pp.: 65-69.*
Ott, R.et al., “An effective method to estimate defect limited yield impact on memory devices”, Advanced Semiconductor Manufacturing Conference and Workshop, IEEE/SEMI , Sep. 8-10, 1999. pp.: 87-91.*
Toshiaki Mugibayashi, et al., “A Novel Quantitative Analysis of Defects Detected by In-Line Monitoring”, ISSM 98, 1998, pp. 335-338.
Hattori Nobuyoshi
Mugibayashi Toshiaki
Levin Naum
Siek Vuthe
LandOfFree
Computer-implemented method of process analysis does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Computer-implemented method of process analysis, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Computer-implemented method of process analysis will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3248039