Computer implemented method of high-level synthesis for the...

Details Computer implemented method of high-level synthesis for the... Computer implemented method of high-level synthesis for the...

2007-03-22

2010-06-22

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07743352

ABSTRACT:
Verification friendly models for SAT-based formal verification are generated from a given high-level design wherein during construction the following guidelines are enforced: 1) No re-use of functional units and registers; 2) Minimize the use of muxes and sharing; 3) Reduce the number of control steps; 4) Avoid pipelines; 5) Chose functional units from “verification friendly” library; 6) Re-use operations; 7) Perform property-preserving slicing; 8) Support “assume” and “assert” in the language specification; and 8) Use external memory modules instead of register arrays.

REFERENCES:
patent: 6324678 (2001-11-01), Dangelo et al.
patent: 6687882 (2004-02-01), McElvain et al.
patent: 7216318 (2007-05-01), Siarkowski
patent: 2003/0182638 (2003-09-01), Gupta et al.
patent: 2004/0230407 (2004-11-01), Gupta et al.

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