Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-09-10
2003-12-30
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C718S001000, C718S001000, C718S001000
Reexamination Certificate
active
06671870
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the design and test of integrated circuit devices, and more particularly, to logic synthesis for improved automatic test pattern generation (ATPG) during the design and test of integrated circuits.
BACKGROUND OF THE INVENTION
The design process for integrated circuits has evolved from a relatively simple process, where relatively few circuits were initially placed onto a circuit layout, to modern complex integrated circuits, where computer aided design (CAD) tools are used to realize a circuit layout. The use of CAD tools to lay out complex integrated circuits, such as application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs), is commonly referred to as electronic design automation (EDA). The only feasible technique for designing, verifying, and testing modern complex integrated circuits is with the use of programmable computer systems that enable a user to realize normal circuit implementations.
One technique for specifying an integrated circuit design is with a hardware description language (HDL) such as VHDL. A hardware description language (HDL) enables representation of an integrated circuit design at a logical level, and provides a high level design language. An integrated circuit is represented in several different levels, comprising different layers of abstraction. Silicon compilers, comprising synthesis programs, are used to yield a final implementation wherein the programs generate sufficient detail to proceed directly to silicon fabrication.
A compiler generates a netlist of generic primitive cells during the processing of an HDL. A netlist is a list of all the nets, or collection of pins needing to be electrically connected, in a circuit. The netlist consists of a detailed list of interconnections and logic components, and can include primitive cells such as XOR gates, NAND gates, latches and D-flip flops and their associated interconnections.
The silicon compiler first generates a netlist of independent cells, then applies a particular cell library to the resulting generic netlist via a process called mapping. As a consequence, a dependent mapped netlist is generated which uses standard circuits that are available within a cell library and which are available to the computer system.
Silicon compilers and mapping programs are well understood in the art, and are described in numerous patents including U.S. Pat. Nos. 5,406,497 and 5,831,868.
Design for testability (DFT) forms an important part of the logic synthesis process. More particularly, design for testability (DFT) involves the up-front consideration of product testability considerations while designing a circuit. Low-cost/high-volume manufacturing has recently dictated that product testability be considered at the onset of circuit design, otherwise products will be inherently hard to test and will cost time and money to achieve desired levels of quality.
Accordingly, numerous programs are known for aiding in the testability process of logic synthesis. For example, it is known to take a mapped netlist that is generated from a silicon compiler, and interchange specific memory cells and circuitry with special memory cells that enable the application of test vectors to specific logic portions of an integrated circuit. The application of such special memory cells in order to apply test vectors to stimulate the design is referred to as a design-for-testability (DFT) implementation.
A number of techniques are known for generating non-exhaustive sets of test patterns that validate functionality and identify faults within a circuit design. Automatic test pattern generation (ATPG) programs are known in the art for providing a reduced size test set while maximizing fault coverage for the design. However, these techniques require a significant test area when integrating design-for-testability (DFT) features since present ATPGs transform regular flip-flop elements into MUX flip-flops elements during a scan insertion whether or not the topology of the circuit requires such substitution. Therefore, a technique is required which significantly decreases the test area cost that is associated with integrating design-for-testability (DFT) features into a circuit design.
SUMMARY OF THE INVENTION
The present invention is a method and an apparatus for implementing automatic test pattern generation (ATPG) with a computer system so as to reduce the area cost when implementing test insertion. More particularly, during scan insertion a field transform is implemented wherein regular flip-flop elements are transformed into MUX flip-flop elements irrespective of the topology of the circuit. However, current topology is considered when identifying already stitched flip-flops by integrating such flip-flops into a scan chain without transforming the flip-flops into MUX flip-flops.
According to one aspect of the invention, a computer implemented circuit synthesis system includes a memory, an automatic test pattern generation (ATPG) algorithm, and processing circuitry. The memory is configured to provide a database, and is operative to store a netlist including nets of an integrated circuit under design. The automatic test pattern generation (ATPG) algorithm is operative to design and test an integrated circuit design. The processing circuitry is configured to reduce layout area used during scan insertion, and is operative to: a) identify logic registers of a proposed integrated circuit design that are stitched as a shift register; b) use the ATPG algorithm to transform identified logical registers into scan equivalent logical registers; c) stitch scan equivalent logical registers in an order in which the scan equivalent logical registers were stitched; d) identify stitched scan equivalent logical registers having a same net on both an SI port and a D port; and e) replace the stitched scan equivalent logical registers having the same net on both the SI port and the D port.
According to another aspect of the invention, a method is provided for reducing area used during test insertion when using an automatic test pattern generator (ATPG) algorithm. The method includes the steps of: identifying a netlist of an integrated circuit which includes nets; identifying a plurality of logical registers of the integrated circuit that are stitched as a shift register; transforming the identified logical registers into scan equivalent logical registers, wherein each scan equivalent logical register has an SI port and a D port; stitching the scan equivalent logical registers following the order in which the scan equivalent logical registers were extracted; and identifying the stitched scan equivalent logical registers having the same net on the respective SI ports and D ports; and replacing the stitched scan equivalent logical registers having the same net on the respective SI ports and D ports with a logical register.
According to yet another aspect of the invention, in an electronic design automation system having a processor, memory and an automatic test pattern generation (ATPG) algorithm for designing and testing an integrated circuit, the logic design of the integrated circuit including nets of the integrated circuit providing a netlist, a method is provided for reducing area used during test insertion when using the ATPG algorithm. The method includes the steps of: providing a netlist associated with an integrated circuit; screening the netlist to identify flip-flop elements that are stitched as a shift register; transforming all the identified flip-flop elements that are stitched as a shift register into respective scan equivalent flip-flop elements with the ATPG algorithm wherein each scan equivalent flip-flop element includes an SI port and a D port; stitching the scan equivalent flip-flop elements following the order in which the scan equivalent flip-flop elements were extracted; and replacing at least one of a plurality of the scan equivalent flip-flop elements having the same net on the SI port and the D port by a flip-flop element.
REFERENCES:
patent:
Bombal Jerome
Ginetti Bernard
Souef Laurent
Koninklijke Philips Electronics , N.V.
Siek Vuthe
Zawilski Peter
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