Computer having multiple address ports, each having logical addr

Details Computer having multiple address ports, each having logical addr Computer having multiple address ports, each having logical addr

1994-12-01

2000-01-04

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711209, 711206, 711207, 711140, 712 2, G06F 1200

Patent

active

060121351

ABSTRACT:
Method and apparatus for a logical address translator which translates a logical address into a physical address in a computer. The computer includes a plurality of address ports. Each address port includes a logical address translator, which includes a plurality of segment-register sets. Each segment-register set holds values which specify address boundaries and translation mapping of a corresponding logical segment. A segment detector is coupled to the plurality of segment-register sets, wherein the segment detector operates to determine whether the logical address is within the specified address boundaries of the logical segment. An address mapper is coupled to the plurality of segment-register sets, wherein the address mapper operates to translate the logical address into a physical address. A translation controller is connected to the segment detector and the address translator, wherein the translation controller operates to output the physical address if the segment detector determines that the logical address is within the specified address boundaries of the logical segment. One embodiment of the segment-register set includes a base address, a limit address, and a physical mapping bias. One embodiment of the computer includes a plurality of address ports, wherein each address port includes a logical address translator.

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Pp. 338-343 of "Structured Computer Organization", Third Edition, by Andrew S. Tanenbaum, 1990.

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