Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2000-08-07
2003-09-16
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S781000
Reexamination Certificate
active
06622279
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a computer for data processing and a method for data processing using a computer.
BACKGROUND INFORMATION
It is already known that reversible codes, particularly Huffman codes, are used for coding information in multimedia applications. This reversible code has the characteristic that a reverse decoding of the trailing code sequence is possible when a forward decoding fails because an error has occurred. Furthermore, synchronization bit sequences with which the end of groups of code words is recognized are inserted for the reverse decoding. In this context, the bit sequence of the code words is turned around by placing a pointer on the starting address of the last code word of the group on the last bit of the code word with the aid of software.
SUMMARY OF THE INVENTION
In contrast, the computer and method according to the present invention have the advantage that, in the case of an error in a code word, groups of code words are prepared for the reverse decoding by a circuit arrangement. The reversal of the bit sequence of the code words of a group by the circuit arrangement in the case of an error saves computing capacity, since then the reversal is carried out in a computing cycle.
It is particularly advantageous that groups of code words are separated by synchronization bit sequences. These synchronization bit sequences are inserted at the earliest point after a previously defined number of bytes. The beginning of the synchronization bit sequence is brought to a uniform byte boundary by so-called padding bits. This permits a simple further processing, particularly the reversal of the bit sequences, by hardware.
It is also advantageous that the computer loads code tables of various reversible and non-reversible codes, in order to decode correspondingly coded information. This yields great flexibility of the codes utilized.
Another advantage is that the computer recognizes the beginning of the groups of data by the synchronization bit sequence.
The computer advantageously recognizes through a counter that all code words or all bits of a group have been decoded. In this manner, the computer recognizes that the remaining bits up to the next synchronization bit sequence are padding bits or the synchronization bit sequence follows directly after the end of the last code word, provided that it adjoins a byte boundary.
REFERENCES:
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patent: 4185302 (1980-01-01), Mounts et al.
Stoldberg et al., Hans-Joachim, “Fast VLD Implementation on V830 RISC Processor,” Information Technology Research Labs, NEC Corp., p. 128.
Berekovic et al., M., “Architecture of a Hardware Module for MPEG-4 Shape Decoding,” Laboratorium für Informationstechnologie, Institut für Theoretische Nachrichtentechnik und Informationsverarbeitung, Universität Hannover.
Berekovic et al., Mladen, “Instruction-Set Extensions for MPEG-4,” Laboratorium für Informationstechnologie, Robert Bosch GmbH, Advanced Multimedia, Universität Hannover.
Bunte Bjoern
Kneip Johannes
Moeller Henning
Runge Holger
Chaudry Mujtaba K.
De'cady Albert
Kenyon & Kenyon
Robert & Bosch GmbH
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