Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2006-01-03
2006-01-03
Le, Dieu-Minh (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S719000
Reexamination Certificate
active
06983402
ABSTRACT:
In a computer device, a latch circuit latches a program read from a ROM. Even when a program C is mistakenly read from the ROM in place of a correct program B, a CPU outputs an access signal to the ROM again to read the program B at the same address from the ROM, and a match detection circuit compares the program B with the program C output from the latch circuit. Since these programs fail to match with each other, the CPU outputs the access signal again. If the ROM outputs the program B correctly this time, the program B matches with the program B output from the latch circuit when the match detection circuit compares these programs. The CPU then executes the program B as correctly read ROM data. Thus, even when a program in the ROM is mistakenly read, safe operation by a correctly read program is ensured.
REFERENCES:
patent: 5157776 (1992-10-01), Foster
patent: 5404467 (1995-04-01), Saba et al.
patent: 5701506 (1997-12-01), Hosotani
patent: 60-225254 (1984-04-01), None
patent: 09-305422 (1997-11-01), None
Matsumoto Masahiko
Yoneda Takashi
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