Computer graphics processing and selective visual display system – Computer graphics display memory system – Multi-port memory
Reexamination Certificate
2005-10-11
2005-10-11
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Multi-port memory
C345S520000, C345S531000, C345S535000, C710S107000
Reexamination Certificate
active
06954209
ABSTRACT:
A core logic chip set in a computer system provides a bridge between processor host and memory buses and a plurality of Accelerated Graphics Port (AGP) buses. Each of the plurality of AGP buses have the same logical bus number. The core logic chip set has an arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each AGP device connected to the plurality of AGP physical buses. Each of the plurality of AGP buses has its own read and write queues to provide transaction concurrency of AGP devices on different ones of the plurality of AGP buses when the transaction addresses are not the same or are M byte aligned. Upper and lower memory address range registers store upper and lower memory addresses associated with each AGP device. Whenever a transaction occurs, the transaction address is compared with the stored range of memory addresses. If a match between addresses is found then strong ordering is used. If no match is found then weak ordering may be used to improve transaction latency times. AGP device to AGP device transactions may occur without being starved by CPU host bus to AGP bus transactions.
REFERENCES:
patent: 5734850 (1998-03-01), Kenny et al.
patent: 5751975 (1998-05-01), Gillespie et al.
patent: 5857086 (1999-01-01), Horan et al.
patent: 5867645 (1999-02-01), Olarig
patent: 5878237 (1999-03-01), Olarig
patent: 5889970 (1999-03-01), Horan et al.
patent: 5923860 (1999-07-01), Olarig
patent: 5937173 (1999-08-01), Olarig et al.
patent: 6006291 (1999-12-01), Rasmussen et al.
patent: 6018810 (2000-01-01), Olarig
patent: 6024486 (2000-02-01), Olarig et al.
patent: 6167476 (2000-12-01), Olarig et al.
patent: 6175889 (2001-01-01), Olarig
patent: 6192455 (2001-02-01), Bogin et al.
patent: 6457121 (2002-09-01), Koker et al.
patent: 6633296 (2003-10-01), Laksono et al.
Bella Matthew C.
Hewlett--Packard Development Company, L.P.
Nguyen Hau
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