Computer circuits, systems, and methods using partial cache...

Details Computer circuits, systems, and methods using partial cache... Computer circuits, systems, and methods using partial cache...

1998-11-05

2001-11-20

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S129000, C711S203000, C711S218000, C711S219000

Reexamination Certificate

active

06321299

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
This application claims a priority right from France Patent Application 09 05420, entitled Circuits, systémés et procédés d'ordinateur utilisant un nettoyage partiel d'une mémoire cache, having inventors Gérard Chauvel, Serge Lasserre, Dominique Benoît Jacques d'Invemo, and filed Apr. 29, 1998.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
The present embodiments relate to computing environments implementing one or more cache memories.
Cache circuits are important components which are frequently used in contemporary computing systems (e.g., microprocessors and the like) to increase system performance by reducing the potential amount of time needed to access information. Typically, a cache circuit includes various components, such as a tag memory which is commonly a random access memory (“RAM”). The tag RAM stores so-called tag information which corresponds to the cached data which is commonly stored in a separate cache data RAM. The tag information may include various characteristics corresponding to the cached data, such as the actual address where the cached data may be found in some other memory device (e.g., an external memory structure). Another component of a cache circuit is the hit detection circuit associated with the tag RAM. The hit detection circuit (of which there are N such circuits in an N-way set associative cache circuit) compares an incoming address with the actual address stored as part of the tag information. If the comparison matches, there is said to be a “hit” in the cache circuit, that is, the data sought at the incoming address may be retrieved directly from the cache data RAM; on the other hand, if the comparison does not match, there is said to be a “miss” in the cache circuit, that is, the data sought at the incoming address is not located, or for some other reason is not reliable, within the cache data RAM. In the event of a cache miss, then the data must be retrieved from a memory higher in the memory hierarchy, such as the main (i.e., often external) memory or in another cache located at a higher level in the system. Thus, access to data following a cache miss requires a greater amount of time then when a cache hit occurs and, indeed, if the access is from external memory the time required may be considerable as compared to the access time in the event of a cache hit.
While the above illustrates that cache memories are generally perceived as beneficial, as computing devices and environments become more complex there is a need to further scrutinize cache operations to determine whether additional efficiency may be achieved. In this regard the present inventors have recognized that a number of clock cycles may be eliminated in the context of certain operations of cache circuits. The reduction of expended clock cycles relating to cache operations improves system speed. In addition, this reduction of clock cycles also reduces overall system power consumption, which is of critical consideration in many contemporary systems such as in portable computing devices.
BRIEF SUMMARY OF THE INVENTION
In one preferred embodiment, there is a method of operating a computing system. The computing system comprises a cache memory, and the cache memory has a predetermined number of cache lines. First, the method, for a plurality of write addresses, writes data to the cache memory at a location corresponding to each of the plurality of write addresses. Second, the method cleans a selected number of lines in the cache memory. For each of the selected number of lines, the cleaning step evaluates a dirty indicator corresponding to data in the line and copies data from the line to another memory if the dirty indicator indicates the data in the line is dirty. Lastly, the selected number of lines which are cleaned is less than the predetermined number of cache lines. Other circuits, systems, and methods are also disclosed and claimed.


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