Electrical computers and digital data processing systems: input/ – Intrasystem connection
Reexamination Certificate
2000-08-31
2004-03-09
Vo, Tim (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
C710S305000, C710S300000, C710S052000
Reexamination Certificate
active
06704817
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method and architecture for managing bus usage to maximize system performance while ensuring reliable bus operation. More particularly, the invention relates to an architecture and system which allows for streaming of reads and writes on a bi-directional bus to reduce bus latency thereby increasing system performance, while ensuring no bus contention and no starvation of reads or writes on the bus.
2. Background of the Invention
Computer systems typically incorporate one or more buses to facilitate communication between devices or components in the system. As used herein, a bus is a plurality of wires or conductors to which multiple agents or devices are coupled in order to transport data or signals among and between the agents or devices. A bi-directional bus provides for reads and writes (i.e., communications in both directions) to occur on common wires or conductors. Typically, a bus has a certain protocol which is to be followed by all of the agents coupled to the bus. Having a consistent protocol ensures all agents use the same rules of communication on the bus.
Since a bus is essentially a group of shared conductors or wires, it is important that the agents share the bus in the manner prescribed by the bus protocol. Moreover, it is important that only one agent drive the bus (i.e., issue or place signals on the shared wires of the bus) at a time. When multiple agents attempt to drive the bus at the same time, it is called a bus conflict or bus contention. Bus contention will often result in the signals or data on the bus being corrupted or unreliable and may also result in damage to the agents on the bus.
To avoid bus contention, dead time or “bubbles” may be introduced on the bus between bus transactions. Bubbles ensure the last transaction is complete before the next transaction is attempted. The use and necessity of bubbles is dictated by the bus protocol which may in turn be dictated by the agents or devices connected to the bus. In some bidirectional buses, for example the RAMbus® a standard memory bus, a bubble is only required for transitions from reads to writes or vice versa. In computer systems employing such bidirectional buses, then, the system must incorporate some mechanism to insert bubbles between read/write transitions to ensure that multiple agents connected to the bus do not attempt to simultaneously drive the bus, i.e., and to ensure there is no bus contention. This bubble or delay time between read/write transitions ensures that the previous transaction, either a read or a write, has ended before the next transaction is attempted. Note that for buses of this type, when the same kind of transaction occurs consecutively on the bus (i.e., consecutive reads or consecutive writes), a delay is not required to ensure there will be no bus contention and thus no bubble is added. Bubbles are only introduced when the bus transactions switch from a read to a write or vice versa.
Although bubbles may be necessary to ensure no bus contention, their occurrence should be minimized because the bubbles result in unused bandwidth that would otherwise be useful to the system for enhanced performance. Specifically, the more bubbles that are introduced, the more wait or delay time that is introduced into the system. Accordingly, a system designers desire to maximize bandwidth and system performance is often at odds with the need to ensure avoidance of bus conflicts by adding bubbles.
One method of reducing the number of bubbles, and the associated delays, would be to stream or group reads and writes together whenever possible. Streaming reads and writes consecutively reduces the number of transitions from reads to writes or vice versa, thereby reducing the number of bubbles required. The system used to group like transactions, however, must also ensure that reads and writes are not indefinitely stalled or starved while a stream of the opposite transaction is being performed on the bus. In particular, the system must ensure read/write fairness and avoid starvation for either.
The present invention is directed at an efficient system and architecture to maximize bandwidth and optimize system performance while avoiding bus contention and read/write starvation.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a novel system and architecture for intelligently managing reads and writes on a bi-directional bus to optimize bus performance, avoid starvation, and introduce bubbles only when needed to avoid bus contention. This is accomplished by separately queuing reads and writes and then using a simple 2 to 1 multiplexer (“mux”) to control the issuance of transactions and bubbles to the bus. The mux is controlled by bus streaming control logic which uses counters, comparators and certain threshold parameters to optimize the system performance by selectively streaming reads and writes together.
The inventive system for managing bidirectional bus usage, comprises: a bi-directional bus; a read queue for pending read bus transactions; a write queue for pending write bus transactions; a mux having a first input coupled to the read queue and a second input coupled to the write queue and an output coupled to the bus; bus streaming control logic coupled to the read queue and the write queue having a first and second control signal coupled to the mux; wherein the bus streaming control logic selectively controls the mux to issue or stream either read transactions from the read queue or write transactions from the write queue to the bus.
In an alternate embodiment of the present invention, the bus streaming control logic of the inventive system further comprises: a first counter to track the number of pending writes in the write queue; a second counter to track the number of consecutive reads issued to the bus; a third counter to track the number of pending reads in the read queue; and a fourth counter to track the number of consecutive writes issued to the bus; as well as a first threshold for pending writes in the write queue; a second threshold for consecutive reads issued to the bus; a third threshold for pending reads in the read queue; and a fourth threshold for consecutive writes issued to the bus.
In an additional alternate embodiment of the present invention, the bus streaming control logic of the inventive system further comprises a plurality of counters to track the number of clock cycles that pending read transactions and write transactions have been waiting in the read queue and the write queue respectively and wherein the bus streaming control logic forces a transition to issue pending transactions which have been waiting for a predetermined amount of time in the queues.
The inventive computer system incorporating the present invention, comprises: a power supply; architecture for managing bi-directional bus usage, comprising: a read queue for pending read bus transactions; a write queue for pending write bus transactions; a mux having a first input coupled to the read queue and a second input coupled to the write queue; bus streaming control logic coupled to the read queue and the write queue having a control signal coupled to the mux; wherein the bus streaming control logic selectively controls the mux to output or stream read transactions from the read queue or write transactions from the write queue.
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Bouchard Gregg A.
Kessler Richard E.
Steinman Maurice B.
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