Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-04-13
2003-08-12
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C714S726000
Reexamination Certificate
active
06606736
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a computer-aided timing adjusting method and apparatus for correcting timing errors (set-up errors and hold errors) by automatically or semiautomatically adjusting the timing of a logic circuit whose layout has been designed, and a storage medium stored with a program for executing this method.
2. Description of the Related Art
In logic circuit, in accordance with its development in integration and with the miniaturizing of its element, a ratio of wiring propagation delay time to gate propagation delay time has been becoming increasingly greater. Therefore, timing analysis for the logic circuit whose layout has been designed is performed with computer.
In the prior art timing adjusting, the designer refers to the gate propagation delay time and wiring propagation delay time of a timing error path, selects a cell to be replaced or a position to be inserted, and performs replacing the cell or inserting a cell.
But, since a signal dull value or a number of error paths in a case where a plurality of timing error paths are overlapped is not taken into consideration, it is difficult to perform timing adjusting effectively.
Also, by replacing or inserting a cell, since the gate propagation delay time and wiring propagation delay time of the cells around it change, timing analysis must be performed again after the net list and layout are renewed to confirm the adjusting result. In repetition of such a processing, since replacing and inserting of cells are manually performed by the designer, timing adjusting takes a long time.
SUMMARY OF THE INVENTION
Accordingly, an object according to the present invention is to provide a computer-aided timing adjusting method and apparatus, and a storage medium stored with a program to execute the method, wherein the timing adjusting is more effectively performed, whereby the adjusting time will be shortened.
In the 1st aspect of the present invention, there is provided a computer-aided timing adjusting method for adjusting a timing in a semiconductor integrated circuit whose layout and wiring have been designed, the semiconductor integrated circuit including sequential circuits, each of the sequential circuits having first and second flip-flops and a combinational circuit connected between an output of the first flip-flop and the input of the second flip-flop, the first and second flip-flops operating in synchronization with a clock, the method comprising the steps of, as shown in
FIGS. 4A through 4C
for example,: preparing a timing error information including the types of timing errors and timing error paths, a delay information relating to signal propagation delay, and a logic information including function and driving capability of each cell in the combinational circuits; when the timing error information has one that the sequential circuit is a set-up error path: selecting a cell which is estimated with referring to the delay information to be the greatest cause for the set-up error arising; searching a cell whose function is the same as the selected cell and driving capability is larger than the selected cell; and replacing the selected cell with the searched cell.
With the 1st aspect according to the present invention, since the ratio of the decreasing amount of path delay time to the increasing amount of the driving capability becomes relatively greater, whereby it will be effective and the timing adjusting time will be shortened.
In the 2nd aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 1st aspect, wherein, in the preparing step, the delay information has input signal dull values of the cells, wherein, in the selecting step, as shown in FIGS.
4
A through
4
C for example, a cell in the proceeding stage of a cell with the largest input signal dull value is selected.
In the 3rd aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 1st aspect, wherein, in the preparing step, as shown in
FIGS. 15A through 15C
for example, the delay information has output-wiring propagation delay times, wherein, in the selecting step, a cell whose output-wiring propagation delay time is the maximum is selected.
In the 4th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 1st aspect, wherein, in the preparing step, the delay information has gate propagation delay times, wherein, in the selecting step, as shown in
FIGS. 16A through 16C
for example, the cell in the proceeding stage of a cell whose propagation delay time is the maximum is selected.
In the 5th aspect of the present invention, there is provided a computer-aided timing adjusting method for adjusting a timing in a semiconductor integrated circuit whose layout and wiring have been designed, the semiconductor integrated circuit including sequential circuits, each of the sequential circuits having first and second flip-flops and a combinational circuit connected between an output of the first flip-flop and the input of the second flip-flop, the first and second flip-flops operating in synchronization with a clock, the sequential circuits having first and second sequential circuits whose combinational circuits have a common part, the method comprising the steps of, as shown in
FIGS. 6A and 6B
for example,: preparing a timing error information including the types of timing errors and timing error paths, and a logic information including function and driving capability of each cell in the combinational circuits; when the timing error information has one that the first and second sequential circuits each are timing error paths: judging whether or not the types of the timing errors of the timing error paths are the same; and if the types are the same, then, in order to lower the degree of the both timing errors, replacing a cell in the common part with a cell, in the logic information, with the same function and a different driving capability, or inserting a cell in the logic information into the common part without changing the function of the common part.
With the 5th aspect according to the present invention, since the timings in the same type and plurality of timing error paths are simultaneously and effectively adjusted, the timing adjusting time will be shortened.
In the 6th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 5th aspect, wherein, as shown in
FIGS. 6A and 6B
for example, if the type of the timing errors is a set-up error, then the replacing or inserting step comprises the steps of: selecting a cell in the common part; searching, in the logic information, a cell having the same function as and a greater driving capability than the selected cell; and replacing the selected cell with the searched cell.
In the 7th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 6th aspect, wherein, in the selecting step, as shown in
FIGS. 6A and 6B
for example, if a plurality of the second sequential circuits exist, then a cell, in the common part, with the largest number of set-up error paths is selected.
In the 8th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 5th aspect, wherein the replacing or inserting step, as shown in
FIGS. 11A and 11B
for example, if the type of the timing errors is a hold error, then comprises the steps of: selecting a cell in the common part; and inserting a cell, in the logic information, before or after the selected cell so as not to change the function as before insertion.
In the 9th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 8th aspect, wherein, in the selecting step, as shown in
FIGS. 11A and 11B
for example, if a plurality of the second sequential circuits exist, then a cell, in the common part, with the largest number of hold error paths is selected.
Kobayashi Tatsuya
Yasue Yoshihiro
Do Thuan
Fujitsu limited
Siek Vuthe
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