Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-02-26
2001-04-10
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S014000, C703S019000
Reexamination Certificate
active
06216255
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a computer-aided logic circuit designing apparatus, a computer-aided circuit designing system, and a computer-aided logic circuit designing method for designing logic circuits using, for instance, hardware description language (HDL) by means of an abstract description method such as a register transfer level (RTL) or the like.
BACKGROUND OF THE INVENTION
In recent years, in association with increase in an integration degree of LSIs, a scale of a circuit on which the LSIs are mounted has been becoming increasingly larger. The HDL is employed for a designing method in association with the tendency for larger scale integration. Because of the tendency, now logic circuits are designed by a plurality of designers each responsible for each block and by means of combining the blocks into one circuit, analyzing a clock system of each block.
When integrating a plurality of blocks into one circuit, if a clock is supplied to a block designed by one person from a block designed by another person and the clock is, for instance, a gated clock, a malfunction may occur in the block designed by the person due to generation of a hazard or for other reasons. In the case as described above, a designer of the block from which a clock is supplied intentionally notifies, in anticipation of the possibility of troubles such as generation of a hazard, a designer of the block to which the clock is supplied of the possibility.
However, if the designer of the block from which the clock is supplied does not notify the designer of the block to which the clock is supplied of the possibility of generation of a hazard or other trouble, or the former designer cannot anticipate the possibility, a trouble may be generated due to a hazard or for other reasons when integrating blocks For this reason, because of inadequate communication between designers or due to shortage of data, a vast quantity of time is required to analyze a cause for a trouble generated when combining blocks, which in return disadvantageously lowers the work efficiency. Especially when an unknown macro or a macro based on unclear specifications is incorporated into a system, and when old resources such as a portion of a net list used previously is used, analysis of the trouble is extremely difficult.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a computer-aided logic circuit designing apparatus, a computer-aided logic circuit designing system, and a computer-aided logic circuit designing method which can notify a designer of troubles in a clock system portion or an asynchronous portion in a logic circuit being designed to improve the work efficiency.
With the present invention, data on a plurality of circuits is combined, a clock system portion is analyzed based on a logic circuit obtained by combining the data, and a result of analysis is displayed differentiating clock systems from each other, so that a trouble generated in a clock system portion in any of a plurality of blocks can clearly be known from a logic circuit being designed, and a long time is not required for analyzing a cause for the trouble, and for this reason the work efficiency can be improved.
With the present invention, data on a plurality of circuits is combined, a clock system portion is analyzed based on a logic circuit obtained by combining the data, a result of the analysis is displayed correlating a clock input element to each type of clock system, so that a trouble relating to a clock input element in a clock system portion in any of a plurality of blocks can clearly be identified from a logic circuit being designed and a long time is not required for analyzing a cause for each trouble, and for this reason the work efficiency can be improved.
With the present invention, data on a plurality of circuits is previously stored, the data on the plurality of circuits is combined, a clock system portion is analyzed based on the logic circuit obtained by combining the data, and a result of the analysis is displayed differentiating clock system types from each other, so that a trouble in a clock system portion in each of a plurality of blocks can clearly be identified from a logic circuit being designed, and a long time is not required for analyzing a cause for the trouble even if a portion or all of old resources is used, and for this reason the work efficiency can be improved.
With the present invention, data on a plurality of circuits is stored, the data on a plurality of circuits is combined, a clock system portion is analyzed based on the logic circuit obtained by combining the data, and a result of the analysis is displayed correlating a clock input element to each type of clock system, so that a trouble relating to a clock input element in a clock system portion of any of a plurality of blocks can clearly be identified from a logic circuit being designed, and a long time is not required for analyzing a cause for the trouble even if a portion or all of old resources is used, and for this reason the work efficiency can be improved.
With the present invention, data on each circuit is modified based on the display result of analysis, so that a work for correcting the trouble can immediately be started after analysis, and for this reason the work efficiency can be improved.
With the present invention, an asynchronous circuit portion is extracted from the logic circuit through analysis of a clock system, and when displaying the result of analysis, an alarm concerning the extracted asynchronous circuit portion is generated, so that the asynchronous circuit portion is clearly identified through the analysis of a clock system and a long time is not required for analyzing a cause for the trouble even in not only the clock system but also the asynchronous circuit portion, and for this reason the work efficiency can be improved.
With the present invention, the data for each circuit is corrected based on a displayed result of analysis to evade hazards in a clock system and for synchronization for an asynchronous circuit portion, so that a work for correcting the trouble in the clock system portion and the asynchronous circuit portion can immediately be started after analysis, and for this reason the work efficiency can be improved.
With the present invention, the analysis result in which data for types of clock system, data on clock input elements, and warning data concerning to troubles in clock systems are correlated to each other is obtained through analysis of the clock system, so that a state of the clock system obtained through analysis of the clock system can easily be checked on the whole.
With the present invention, a clock path for each type of clock system is further correlated to data for types of clock system, data on clock input elements, and warning data concerning troubles in clock systems, so that a state of combining clock paths between blocks can easily be checked.
With the present invention, each client designs data on a circuit having a clock system portion, sends a request for analysis of data on the designed circuit to the server, and displays a result of analysis reported from the server after a request for analysis is sent differentiating clock systems from each other; and the server combines data on circuits sent from the plurality of clients respectively upon the request, analyzes a clock system portion based on a logic circuit obtained by combining the data, and reports the result of analysis to the plurality of clients, so that the server can centralize management of troubles in the clock system portion in any of the plurality of blocks from a logic circuit being designed in each client, and there is no load to analyze a cause for the trouble by a client side, and for this reason the work efficiency in the entire system can be improved.
With the present invention, each of the clients designs data on a circuit having one or a plurality of clock input elements each constituting a clock system portion, sends a request for analysis of data on the designed circuit to the
Ito Yasushi
Kirinaka Masaki
Komatsu Shinpei
Kubono Chika
Tobita Tatsushi
Fujitsu Limited
Kik Phallaka
Smith Matthew
Staas & Halsey , LLP
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