Computer aided design systems and methods with reduced...

Details Computer aided design systems and methods with reduced... Computer aided design systems and methods with reduced...

2006-06-13

2006-06-13

Whitmore, Stacy A. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C711S133000

Reexamination Certificate

active

07062727

ABSTRACT:
Methods, systems, software products analyze a circuit design with reduced memory utilization. Access to at least one block of the circuit design is detected. If the one block is not loaded within a circuit model of computer memory, a determination is made whether loading the one block into the circuit model would exceed a predefined maximum utilization of the computer memory. If loading the one block into the circuit model would exceed the predefined maximum utilization, one or more blocks from the circuit model are unloaded and the one block is loaded into the circuit model. If loading the one block into the circuit model would not exceed the predefined maximum utilization, the one block is loaded into the circuit model.

REFERENCES:
patent: 4654819 (1987-03-01), Stiffler et al.
patent: 5249133 (1993-09-01), Batra
patent: 5301318 (1994-04-01), Mittal
patent: 5668732 (1997-09-01), Khouja et al.
patent: 5673420 (1997-09-01), Reyes et al.
patent: 5682320 (1997-10-01), Khouja et al.
patent: 5696694 (1997-12-01), Khouja et al.
patent: 5812416 (1998-09-01), Gupte et al.
patent: 5825660 (1998-10-01), Cagan et al.
patent: 5831869 (1998-11-01), Ellis et al.
patent: 5838579 (1998-11-01), Olson et al.
patent: 5903476 (1999-05-01), Mauskar et al.
patent: 5946218 (1999-08-01), Taylor et al.
patent: 5949691 (1999-09-01), Kurosaka et al.
patent: 6028991 (2000-02-01), Akashi
patent: 6075932 (2000-06-01), Khouja et al.
patent: 6185722 (2001-02-01), Darden
patent: 6230299 (2001-05-01), McSherry et al.
patent: 6256711 (2001-07-01), Berliner
patent: 6272671 (2001-08-01), Fakhry
patent: 6308301 (2001-10-01), McBride et al.
patent: 6308304 (2001-10-01), Devgan et al.
patent: 6330703 (2001-12-01), Saito et al.
patent: 6345379 (2002-02-01), Khouja et al.
patent: 6363516 (2002-03-01), Cano et al.
patent: 6378123 (2002-04-01), Dupenloup
patent: 6480987 (2002-11-01), McBride
patent: 6490717 (2002-12-01), Pederson et al.
patent: 6493864 (2002-12-01), Liu
patent: 6523149 (2003-02-01), Mehrotra et al.
patent: 6526562 (2003-02-01), Haddad et al.
patent: 6529861 (2003-03-01), Patra et al.
patent: 6531923 (2003-03-01), Burns
patent: 6587999 (2003-07-01), Chen et al.
patent: 6598211 (2003-07-01), Zachariah et al.
patent: 6618834 (2003-09-01), Takeyama et al.
patent: 6751782 (2004-06-01), Levin et al.
patent: 6772404 (2004-08-01), Tanaka
patent: 6801884 (2004-10-01), Ferreri et al.
patent: 6807520 (2004-10-01), Zhou et al.
patent: 6836877 (2004-12-01), Dupenloup
patent: 6931613 (2005-08-01), Kauth et al.
patent: 2002/0002701 (2002-01-01), Usami et al.
patent: 2002/0010901 (2002-01-01), Otaguro
patent: 2002/0023255 (2002-02-01), Kamiewicz
patent: 2002/0144219 (2002-10-01), Zachariah et al.
patent: 2003/0051222 (2003-03-01), Williams et al.
patent: 2003/0200519 (2003-10-01), Argyres
patent: 2003/0208721 (2003-11-01), Regnier
patent: 2003/0221173 (2003-11-01), Fisher
patent: 2003/0237067 (2003-12-01), Mielke et al.
patent: 2004/0044972 (2004-03-01), Rohrbaugh et al.
patent: 2004/0078767 (2004-04-01), Burks et al.
patent: 2004/0199880 (2004-10-01), Kresh et al.
patent: 2005/0027954 (2005-02-01), Rothman et al.
patent: 07334532 (1995-12-01), None
Keller, S. Brandon; Rogers, Dennis R.; Lelm, Charles A.; U.S. Appl. No. 10/706,682, Entitled: Method And Program Product For Determining Nets Requiring Detailed Electromigration And Self Heating Analysis In A Digital Integrated Circuit; Filed Nov. 12, 2003.
Keller, S. Brandon; Rogers, Dennis R.; Lelm, Charles A.; U.S. Appl. No. 10/706,698, Entitled: Method and Program Product For Performing Self-Heating Analysis In A Digital Integrated Circuit Through A Single Cycle Transient Simulation; Filed Nov. 12, 2003.
Keller, S. Brandon; Rogers, Dennis R.; Lelm, Charles A.; U.S. Appl. No. 10/706,376, Entitled: Method And Program For Visual Display and One-Click Repair Of Electromigration And Self Heating Design-Rule Violations In A Digital Integrated Circuit Layout Database; Filed Nov. 12, 2003.
Keller, S. Brandon; Rogers, Dennis R.; Lelm, Charles A.; U.S. Appl. No. 10/706,501, Entitled: Method And Program Product For Performing Electromigration Analysis In A Digital Integrated Circuit By Converting A Netlist To A DC Model And Performing DC Analysis Of The DC Model; Filed Nov. 12, 2003.
Keller, S. Brandon; Rogers, Dennis R.; Lelm, Charles A.; U.S. Appl. No. 10/706,526, Entitled: Method And Program Product For Performing A Worst Case Electromigration And Self Heating Analysis In A Digital Integrated Circuit With Worst-Case Superposition Of Partial Currents; Filed Nov. 12, 2003.
Keller, S. Brandon; Rogers, Dennis R.; Lelm, Charles A.; U.S. Appl. No. 10/706,692, Entitled: Method And Program Product For Performing Electromigration Analysis In A Digital Integrated Circuit Through A Single Cycle Transient Simulation; Filed Nov. 12, 2003.
Keller, S. Brandon; Rogers, Dennis R.; Lelm, Charles A.; U.S. Appl. No. 10/706,508, Entitled: Method And Program Product For Performing Self-Heating Analysis In A Digital Integrated Circuit Layout Database by Substituting Resistive Models For Active Devices; Filed Nov. 12, 2003.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655516US; Entitled: Method And Program Product For Determining Worst Case Currents In A Digital Integrated Circuit Through Worst-Case Superposition Of Partial Currents; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655564US; Entitled: Systems And Methods For Re-Using Circuit Design Analysis Results; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655581US; Entitled: System And Method For Determining Detail Of Analysis In A Circuit Design; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655595US; Entitled: Systems And Methods That Identify Equivalent Instantiation-Specific Configuration Information For Analysis Tools; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H. & Stevens, Scott Alan; U.S. Patent Application filed under EV210655520US; Entitled: System And Method To Limit Analyzed Current Flow In A Circuit Design; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655533US; Entitled: System And Method For Processing Configuration Information; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655555US; Entitled: System And Method For Balancing Run-Time And Result Accuracy In A Circuit Design Analysis Tool; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655578US; Entitled: System And Method For Indicating Logic State Combinations Used During Circuit Design Analysis; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655547US; Entitled: System And Method For Determining Control Signal Combinations For Use During Simulation Of A Stage Of A Circuit Design; Filed Jan. 30, 2004.

Affiliated with

Also associated with

Rating

Computer aided design systems and methods with reduced... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Computer aided design systems and methods with reduced..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Computer aided design systems and methods with reduced... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3659597