Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-12-05
2003-11-04
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06643835
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a computer-aided design supporting system for arranging cells independently with reference to a cell library.
2. Description of the Related Art
To design a semiconductor circuit, a computer-aided design supporting system is often used to automatically arrange and connect function blocks or “cells”. Such a computer-aided design supporting system is disclosed in, for example, Japanese Laid Open Patent Application (JP-A-Heisei 6-85062). In this reference, the computer-aided design supporting system has a cell library, which stores patterns of circuits such as basic gates and logic circuits, which have a high use frequency as standard cells. The standard cell is composed of a logic circuit section, a power supply section and a ground section.
FIG. 1
shows the structure of the conventional computer-aided design supporting system
100
. The design supporting system
100
is composed of a CAD tool
101
and a cell library
102
. The CAD tool
101
is composed of an arranging tool
103
and a wiring tool
104
.
The CAD tool
101
carries out automatic arrangement and connection of the cells. The cell library
102
is a database in which various standard cells are registered. The arranging tool
103
reads out the standard cells from the cell library
102
and automatically arranges the read out standard cells on a cell track provided in an arrangement region. The wiring tool
104
automatically connects between the standard cells on the cell track and between the standard cells and wiring lanes on a wiring track in the arrangement region.
FIG. 2
shows the structure of a conventional standard cell
110
. As shown in
FIG. 2
, the standard cell
110
is composed of a power supply section
111
, a logic circuit section
112
, and a ground section
113
. The standard cell
110
is arranged on the cell track, using the power supply section
111
, the logic circuit section
112
and the ground section
113
as a unit.
FIGS. 3A
to
3
C show the arrangement of the conventional standard cells.
FIG. 3A
shows the state in which three standard cells
110
a
are arranged on a cell track T
10
, and three standard cells
110
b
are arranged on a cell track T
11
. The ground sections
113
b
of the standard cells
110
b
overlap the ground terminal sections
113
a
of the standard cells
110
a.
Thus, the ground sections
113
b
of the standard cells
110
b
are arranged on the cell track T
10
.
When a wiring track T
12
should be provided between the cell track T
10
and the cell track T
11
after the standard cells
110
a
and
110
b
have been arranged, the overlapping of the ground terminal sections
113
a
and the ground terminal sections
113
b
are first eliminated, as shown in FIG.
3
B. Then, the region of the cell track T
11
is moved, so that the wiring track T
12
is formed, as shown in FIG.
3
C.
If the power supply sections or the ground sections are arranged between the adjacent cell tracks such that they are used in common, the arrangement region will be used more effectively. If a wiring track should be arranged between the cell tracks, the power supply sections or the ground sections are independently arranged. In this case, however, the arrangement region cannot be utilized effectively.
Also, it is desired that the height of the power supply section or ground section, namely, the dimension in the direction in which the power supply section and the ground section are aligned in the standard cell, can be selected optionally. Also, it is desirable that the amount of current that flows in the standard cell can be selected optionally. For this purpose, it is necessary to provide a plurality of standard cells for every logic circuit. The standard cells are different power supply sections and different ground sections in height and permissible current value. For this reason, a great number of standard cells need to be registered in the cell library, so that a selecting operation of standard cells is complicated in case of arrangement of the standard cell.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a computer-aided design supporting system in which power supply cell patterns, logic cell patterns and ground cell patterns can be arranged individually and independently.
Another object of the present invention is to provide a computer-aided design supporting system in which an arranged power supply cell pattern, an arranged logic cell pattern and an arranged ground cell pattern are automatically connected to each other.
Still another object of the present invention is to provide a computer-aided design supporting system in which an arranged power supply cell pattern, an arranged logic cell pattern and an arranged ground cell pattern constitutes a pattern of a logic device as a unit.
Yet still another object of the present invention is to provide a computer-aided design supporting system in which an arranged power supply cell pattern, an arranged logic cell pattern and an arranged ground cell pattern can be changed or moved as a unit.
It is an object of the present invention to provide a computer-aided design supporting system in which a cell track and a wiring track can be effectively arranged.
In order to achieve an aspect of the present invention, a computer-aided design supporting system for a semiconductor device includes a cell library, an arranging tool and a wiring tool. The cell library stores a plurality of logic cell patterns, a plurality of power supply cell patterns, and a plurality of ground cell patterns. A logic device pattern of the semiconductor device includes one of the plurality of logic cell patterns, one of the plurality of power supply cell patterns, and one of the plurality of ground cell patterns. The arranging tool arranges selected ones of the plurality of logic cell patterns, selected ones of the plurality of power supply cell patterns and selected ones of the plurality of ground cell patterns on cell tracks individually and independently in response to an arrange instruction. The wiring tool connects between the selected logic cell patterns, between the selected power supply cell patterns and between the selected ground cell patterns arranged on the cell tracks in response to a wiring instruction to form a pattern of the semiconductor device.
Here, a pattern of a specific logic device may include a specific one of the selected logic cell patterns, a specific one of the selected power supply cell patterns and a specific one of the selected ground cell patterns. Also, it is supposed that after one of the specific logic cell pattern, a specific power supply cell pattern and a specific ground cell pattern is arranged by the arranging tool, another may be arranged by the arranging tool with respect to the one cell pattern. In this case, the one cell pattern and the other cell pattern are automatically connected.
Also, it is desirable that the plurality of power supply cell patterns are grouped in a plurality of groups, and the plurality of ground cell patterns are grouped in a plurality of groups. In this case, the plurality of groups for the plurality of power supply cell patterns may be different from each other in at least one of a height of cell pattern, the number of power supply lines, and a permissible current value. In addition, the plurality of groups for the plurality of ground cell patterns may be different from each other in at least one of a height of cell pattern, the number of ground lines, and a permissible current value.
Also, the arranging tool may include a logic cell tool, a power supply cell tool and a ground cell tool. The logic cell tool arranges each of the selected logic cell patterns on either of the cell tracks in response to a logic cell arrangement instruction. The power supply cell tool arranges each of the selected power supply cell patterns on either of the cell tracks in response to a power supply cell arrangement instruction. The ground cell tool arranges each of the selected ground cell patterns on eith
Kozai Atsuko
Matsumoto Takeshi
NEC Electronics Corporation
Siek Vuthe
LandOfFree
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