Computer aided design flow to locate grounded fill in a...

Details Computer aided design flow to locate grounded fill in a... Computer aided design flow to locate grounded fill in a...

2000-05-25

2002-12-24

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06499135

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the design of integrated circuits. More particularly, the present invention relates to designing grounded fill elements in a large scale integrated circuit using computer aided design (CAD).
2. Background
Large scale central processing unit (CPU) integrated circuit computer chips increasingly contain more transistors and more metal layers. At the same time, the feature size of wires and other chip components is getting smaller as the enabling technologies improve. Because of increased chip complexity, chip designers and manufacturers are encountering challenges that they did not have to address in the design and manufacture of less complex chips.
FIG. 1
is a cross-section diagram showing an integrated circuit chip having seven metal layers in accordance with the prior art (not to scale). The chip includes a wafer (
10
). A dielectric layer (
12
) is formed on the wafer. The first metal layer, or metal
1
(
14
) is deposited next. Metal
2
(
18
), metal
3
(
20
), metal
4
(
22
), metal
5
(
24
), metal
6
(
26
) and metal
7
(
28
) are successively deposited. Dielectric layers (
16
,
30
,
32
,
34
,
36
,
38
,
40
) separate the metals. The chips are grown from the wafer on up. Therefore, for example, it can be said that metal
4
(
22
) is the upper adjacent layer to metal
3
(
20
) and that metal
2
(
18
) is the lower adjacent layer to metal
3
(
20
). Each metal layer contains etched wires including conductors (at V
dd
) and ground wires (at V
ss
). Generally, the metal layers are thicker at the top of the chip.
Integrated circuit chips require multilayer interconnects to connect various transistors to complete a circuit. In the metal layers of an IC chip, there are some areas with high interconnect density and others with low density. Due to this variation in density, excessively polishing may result in low density areas during the chemical mechanical polishing (CMP) process. In order to avoid this issue, dummy metal is inserted in the design to make the interconnect density in a layer uniform.
When dummy metal is included in a chip design without further consideration, it will be electrically floating and will capacitively couple with the signal lines above and below. It would therefore be desirable to connect dummy metal to ground, thereby avoiding unwanted noise in the chip.
Computer Aided Design (CAD) is used extensively in the design of computer chips. Many CAD tools are commercially available. However, commercially available CAD tools suffer from limitations of memory and processing speed, so that optimal design of grounded fills in a chip is not possible by merely using off-the-shelf CAD tools.
It is therefore desirable to improve on existing CAD tools to allow for better design of grounded fills within a large scale integrated circuit chip. Such improved CAD tools and systems result in integrated circuits not achievable using previous technologies.
BRIEF DESCRIPTION OF THE INVENTION
For an integrated circuit having multiple metal layers, a computer-aided design (CAD) method for designing grounded fill in the integrated circuit includes: (a) finding the eligible fill areas for each metal layer; (b) storing the eligible fill area data for each metal layer in an overflow memory; (c) finding ground contact areas for each metal layer; (d) storing the ground contact area data for each metal layer in an overflow memory; (e) temporarily storing the eligible fill area data for a selected metal layer and the ground contact area data for the metal layers adjacent to the selected metal layer in active memory; (f) fitting a fill pattern to an eligible fill area in the selected metal layer, where the fill pattern is composed of at least one element; (g) checking the adjacent metal layers for a ground contact where the element of the fill pattern may be grounded; (h) locating a conductive via between the element of the fill pattern and a ground contact in an adjacent layer; and (i) repeating steps (e) through (h) for each metal layer.


REFERENCES:
patent: 5636133 (1997-06-01), Chesebro et al.
patent: 5763955 (1998-06-01), Findley et al.
patent: 5923563 (1999-07-01), Lavin et al.
patent: 6305000 (2001-10-01), Phan et al.

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