Computer address translation using fast address generator during

Details Computer address translation using fast address generator during Computer address translation using fast address generator during

1997-08-04

1999-09-28

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Generating prefetch, look-ahead, jump, or predictive address

711202, 711204, 711206, 711209, G06F 1210

Patent

active

059604662

ABSTRACT:
An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a linear address space. A paging mechanism optionally maps linear addresses into physical or real addresses. Independent protection of address spaces is provided at each level. Information about the state of real memory pages is kept in segment registers or a segment register cache potentially enabling real memory access to occur simultaneously with address calculation, thereby increasing performance of the computer system.

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DPS-8 Assembly Instructions, Honeywell Corporation, Apr. 1980, Chapters 3 and 5.

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