Computer address translation system and method for converting ef

Details Computer address translation system and method for converting ef Computer address translation system and method for converting ef

1997-09-30

1999-10-26

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711208, 711220, 711203, 711168, G06F 1210, G06F 1206

Patent

active

059745207

ABSTRACT:
A computer address translation method and system applicable in CPUs for translating an effective address and a selector address into a physical address under the control of an invalidity signal through a translation lookaside buffer having a stored first address and a stored second address. An effective address and a selector address are simultaneously input to the translation lookaside buffer such that address translation and linear address production are parallel processed, thereby effectively speeding up the address translation process.

REFERENCES:
patent: 5233553 (1993-08-01), Shak et al.
patent: 5255377 (1993-10-01), Feldman
patent: 5517657 (1996-05-01), Rodgers et al.
patent: 5652872 (1997-07-01), Richter et al.
patent: 5664159 (1997-09-01), Richter et al.
patent: 5701448 (1997-12-01), White
patent: 5860154 (1999-01-01), Abramson et al.

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