Computer

Details Computer Computer

2000-08-11

2003-08-05

Lefkowitz, Sumati (Department: 2189)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S305000, C710S301000

Reexamination Certificate

active

06604164

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to a computer with several insert cards or adapter cards (hereafter referred to as “adapter cards”).
Computers with several adapter cards are known. They have bus segments that are adjacent to each other and into which the adapter cards are placed. Any adapter cards with the appropriate bus specifications can be inserted into the insertion slot, and at least one adapter card must have a CPU or a computer module. This adapter card is designated as the host, while the other adapter cards are designated utility adapter cards or blind adapter cards, which are configured as needed to accommodate various uses or applications.
A bus system that is increasingly widely used, representing a further development of the PCI-bus, is the so-called compact PCI-bus. This bus has, according to standards, eight insertion slots, so that by employing one CPU, seven utility insertion slots remain. This can be too few for any given use or application. It has therefore been proposed that the bus speed be reduced to realize a greater number of insertion slots with longer bus segments. This, however, is undesirable since it reduces the throughput of the system.
CPU units have already been developed which require two insertion slots, each serving a separate bus segment, since in such a configuration 14 utility insertion slots can be utilized. This solution, however, does not permit hot-swap operation and provides no redundancy.
Demanding applications frequently require an especially high availability of the computer. For such applications, two CPU adapter cards are often installed, such that upon failure of one of them the other card can perform the central computing functions alone.
To combine high availability and correspondingly high failure protection with an increased number of available insertion slots, the use of a bridge circuit has been proposed. In this proposal, a bridge board combines two CPU cards with two I/O-units that are offset with respect to the surface of the motherboard or the backplane, which overlap both bus segments.
Irrespective of how the CPU cards and the I/O cards are arranged over the four insertion slots of the daughterboard and the opposing insertion slots in the motherboard, exceptional demands are placed on the I/O cards, which must perform a number of additional functions when the corresponding CPU cards fail. Both CPU cards could in fact be arranged on one segment and the I/O input cards on the other segment, which would be a less complex implementation. However, in normal use such a solution is worse because a symmetric load for both bus segments cannot be attained, and special additional signal lines are required that do not conform to standards, raises compatibility problems.
In view of these difficulties, it has also been proposed to replace both I/O cards with CPU cards, resulting in four CPU cards. This solution provides a very good data throughput and a symmetric load distribution. On the other hand, it is the most expensive feasible solution.
BRIEF SUMMARY OF THE INVENTION
It is therefore a main objective of the invention to provide a computer which has several adapter cards that are insertable in a plurality of adjacent bus segments, which combines high availability with an increased number of available utility insertion slots at favorable cost.
According to one aspect of the invention, high availability is attained by hard-wiring an I/O-unit and a CPU-unit in such a way that the combined units can be removed and replaced with another one while the computer is in operation. This is often referred to as hot-swapping.
To achieve the configuration of the invention, the signal lines of both bus segments in the motherboard/backplane are routed in an overlapping (interleaved) manner at the fringes of both bus segments. Thus, if the bus segments are identified as “A” and “B”, then the connectors, that is, the connection elements for inserting the cards in the motherboard, are linked in the motherboard/backplane as follows:
AAAAAAABABBBBBBB.
Preferably, identical connectors can be used at all positions of the bus elements.
The hard-wiring and a mechanically well-supported slide guide of a bridge member of this type do not guarantee that the contacts of the I/O-unit and CPU-unit in the backplane release simultaneously or, during insertion, make simultaneous contact. The chronological sequence of a hot-swap is simplified by providing an individual hardware connection to the motherboard for each unit. However, the beginning and the end of the hot-swap process are determined for the bridge member as a whole.
According to the invention, two independent bridge members are provided, each forming an adapter card with an I/O-unit or CPU-unit and internally electrically linked through a daughterboard. In accordance with the invention, the I/O-unit of one bridge member is inserted in one bus segment, but the CPU-unit of the same bridge member is inserted in the other bus segment. The I/O-unit of the other bridge member is also linked with the one bus segment, and the CPU-unit of the other bridge member is also linked with the other bus segment.
In this manner, standard signals and connections for compact PCI-buses can be used, which represents a particular advantage of the invention. It is possible without further difficulty to use separate address spaces for each bus segment. Each CPU communicates with a bus segment so that a very direct realization is possible. Initialization of the two CPUs differs in that one CPU is linked with the appropriate bus segment over an I/O-unit, while the other CPU is linked directly with the appropriate bus segment. This solution provides 12 utility insertion slots and two CPU adapter cards which can be hot-swapped, while signal utilization of the bus lines does not deviate from standards.
The bridge members—in addition to the local system bus—transmit the necessary signals and ensure, when necessary, an energy supply which makes hot-swapping of the CPU and I/O-unit link (bridge member) possible. These links guarantee that the internal current supply of the link is not turned on before both components have been completely inserted. In one embodiment, leading pins are used to provide current from the bridge circuit of the other unit.
The CPU card and I/O card, which are linked across the local bus or a bus circuit, form a structural unit or a bridge member. The connections to both bus segments can be structurally alike and symmetric. In a typical embodiment, the “host” function of both bus segments is provided by the card of the bridge member which contacts both. This allows the separation of the other (inactive) bridge member from both bus segments.
A rearrangement of the host configuration when the roles of the bridge members as host and non-host are exchanged occurs simultaneously on both bus segments. This allows the removal of the bridge member that is configured as non-host (secondary host) from the system by hot-swapping. A bridge member inserted by hot-swapping is pre-set as non-host (secondary host) for both bus segments.
One embodiment of the invention provides that in a particular mode of operation each bridge member becomes a host for a respective bus segment. To support a hot-swap, this mode of operation is switched to the above-mentioned mode of operation and configuration.
Further details, advantages and characteristics of the invention are set forth in the following description of an exemplary embodiment with reference to the drawings.


REFERENCES:
patent: 4654784 (1987-03-01), Campanini
patent: 4777615 (1988-10-01), Potash
patent: 5225967 (1993-07-01), Carteau
patent: 5674077 (1997-10-01), Flaig et al.
patent: 5852725 (1998-12-01), Yen
patent: 5991844 (1999-11-01), Khosrowpour
patent: 6195717 (2001-02-01), Henderson et al.
patent: 6473822 (2002-10-01), Nakamatsu et al.
patent: 0410861 (1991-01-01), None
patent: WO 89/07349 (1989-08-01), None

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