Compute node to mesh interface for highly scalable parallel...

Details Compute node to mesh interface for highly scalable parallel... Compute node to mesh interface for highly scalable parallel...

2006-05-09

2006-05-09

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S141000, C711S146000, C711S151000, C710S040000, C710S112000, C710S306000, C710S244000

Reexamination Certificate

active

07043612

ABSTRACT:
An interface circuit for interfacing one or more compute nodes to a mesh and for serving a wide range of MPP systems and a method for exchanging data between a first agent on an expansion bus and a second agent on a system bus through a bus bridge so as to maintain cache coherency with data cached by one or more agents on the system bus. Transaction requests are queued within the bus bridge, transactions are snooped on the system bus, and a record of pending transaction addresses is maintained. Issuance of a queued transaction having the same cache line address as a pending transaction is stalled until the pending transaction has been completed.

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patent: 6351791 (2002-02-01), Freerksen et al.
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